In this paper, we design and manufacture a flanged double ridged waveguide with a tapered section as a sample holder for measuring the electromagnetic shielding effectiveness (SE) of planar material in broadband frequency ranges up to 10 GHz. The proposed technique overcomes the limitations of the conventional ASTM D4935 test method at high frequencies. The simulation results for the designed sample holders agree well with the fabricated ones in consideration of the design specification of S11 < -20 dB within the frequency range of 1-10 GHz. To verify the proposed measurement apparatus, the measured SE data of the commercial shielding materials from 1 to 10 GHz were indirectly compared with those obtained from the ASTM D4935 from 30 MHz to 1 GHz. We observed that the SE data obtained by using both experimental techniques agree with each other.

In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.

A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-µm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique.

This paper proposes a novel sequential coherent preambleless demodulator that uses phase signals instead of complex signals in the automatic frequency control (AFC) and carrier recovery circuits. The proposed demodulator employs a phase-combined frequency error detection circuit and dual loop AFC circuit to achieve fast frequency acquisition and low frequency jitter. It also adopts an open loop carrier recovery scheme with a sample hold circuit after the carrier filter to ensure carrier signal stability within a packet. It is shown that the frame error rate performance of the proposed demodulator is superior, by 30%, to that offered by differential detection in a frequency selective Rayleigh fading channel. The hardware size of the proposed demodulator is about only 1/10 that of a conventional coherent demodulator employing complex signals.