This paper considers wide-sense nonblocking operation of the Wavelength-Space-Wavelength elastic optical switch. Six control algorithms, based on functional spectrum decomposition in interstage links and functional decomposition of center stage switches, are proposed for two switching fabric architectures. For these algorithms we derived wide-sense nonblocking conditions and compared them with strict-sense nonblocking ones. The results show that the proposed algorithm reduces the required number of frequency slot units (FSUs) or center stage switches, depending on the switching fabric architecture. Savings occur even when connections use small number of frequency slot units.

Telecommunication networks have evolved from telephony networks to the Internet, and they sustainably support the development of a secured, safe, and comfortable society. The so-called “switching technology” including the evolved “network system technology” is one of the main infrastructure technologies used for realizing information communication services. On the occasion of completion of 100 years since the establishment of the IEICE, we summarize the history of network system technologies and present their future direction for the next generation. We mainly focus on a series of technologies that evolved through the discussions of the IEICE technical committees on switching engineering, launched 50 years ago, switching systems engineering, and network systems in action.

In this paper, we consider a switching system modeled by a discrete-time flow model. By simulation, it is shown that a lot of border-collision bifurcations occur since the system is piecewise linear. By using its characteristics, we classify its dynamics into modes, and we define blocks and a kind of Poincare map based on the modes. We calculate occurrence conditions of each block and all the Poincare points by computer-assisted analysis. We consider two bifurcation phenomena, and we show that a Poincare point hits a boundary of the occurrence conditions of a block. So, both bifurcations are indeed border-collision bifurcations.

The uniform switching system is the family of non-linear n m binary arrays constrained such that all columns are from the constant weight k vectors and all rows have weights divisible by p > 0. For this system, we present a cardinality formula and an enumerative algorithm.

Broadband subscriber loop system and ATM switching system are the key equipment for construction of Broadband networks. In this paper, we describe the architecture of access network and the implementation of ATM switching system with multi-service interface for construction of broadband access network. We also represent the design of MAIN-AN (Multi-service Access Integrated Network--Access Node) system as integrated access network platform which enables to accommodate ATM/SDH-based and ATM/PON-based FTTx (Fiber-To-The-x) access architecture simultaneously. The system has a Cross-point ATM Switch Fabric with 10 Gbits/sec throughput and it has been implemented using 0.5 µm CMOS technology. For performance evaluation of it, we simulate it under burst traffic conditions. In addition, we show the implementation of prototype of ASIC (Application Specific Integrated Circuit), MAIN system and its core PBA (Printed circuit Board Assembly) and so on.

An ATM buffer management scheme with logically separated buffers is proposed to guarantee various Quality of Services such as CBR, rt-VBR, nrt-VBR, ABR, and UBR and to make efficient use of system resources in ATM switching systems. By assigning proper priorities based on the count indicator (CI) and the time indicator (TI), respectively, the scheme can afford ABR services without cell loss and real-time services with controllable delay.

In this paper a high-performance copy network named PPCN is proposed for large scale ATM switching systems. The proposed copy network consists of multiple planes of the P2I Copy Networks(PCN) arranged in parallel. The PCN planes are designed based on the P2I multistage interconnection networks (MINs). A single PCN plane is itself a preliminary self-routing copy network which, however, is not a non-blocking one. A novel dispatcher is designed to dispatch input cells to the PCN planes such that no internal blocking nor output contention arises during the cell replication procedure and the offered load can be shared in an efficient way. The architecture of the PPCN provides flexibility for the maximum fanout for an input cells. In a PPCN system, the maximum fanout for an input cells is determined only by the number of interconnection stages within the PCN planes, independent of the input size of the system. The performance of the PPCN is studied under uniform traffic. It is shown that a small constant number of PCN planes are sufficient for a PPCN system to achieve an acceptable low overflow probability regardless of the system size. The hardware complexity of an N N PPCN is O(N log2 K) and the length of the routing tag is O(log2 K) bits, where K is the maximum fanout for an input cell. The storage complexity of the translation tables adopted in an N-inlet PPCN is O(N), which is much lower than that of the previously proposed ones.

The small planar packaging (SPP) system described here can be combined with card-on-board (COB) packaging in high-speed asynchronous transfer mode (ATM) switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density, high packaging density and high cooling capability. Prototype SPP system with air flow control structure for switching MCMs is constructed. Each MCM contained a 35 array of low thermal resistance butt-lead pin-grid-array on a glass ceramic substrate measuring 100170 mm with a plate fin heat-sink. This allows a power dissipation of more than 125 W per MCM, and 300 W per printed circuit board (PCB). Obtained board level heat flux density of the SPP system is 0. 37 W/cm2, which is six times that of conventional COB packaging. The SPP system combined with the COB packaging provides a small system foot-print and compact hardware for high-speed, large capacity ATM switching systems. This high-performance air cooling technology will be especially useful for future broadband ISDN high-speed switching systems.

An innovative small planar packaging(SPP)system is described that can be combined with card-on-board(COB)packaging in high-speed asynchronous transfer mode switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density and high packaging density, combining the advantages of both planar packaging used in computer systems and COB packaging used in telecommunication systems. Using a newly developed quasi-coaxial zero-insertion-force connector, point-to-point 311 Mb/s of 8-bit parallel signal transmission is achieved in an arbitrary location on the SPP systems shelf. Also about 5400 I/O connections in the region of the planar packaging system are made, thus the SPP system effectively eliminates the I/O pin count limitation. Furthermore, the heat flux management capability of the SPP system is five times higher than of conventional COB packaging because of its air flow control structure. An SPP system can easily enlarge the switch throughput and it will be useful for future high-speed, high-throughput ATM switching systems.

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

A neural network approach called the "Gradual Neural Network (GNN)" for the time slot assignment problem in the TDM multicast switching system is presented in this paper. The goal of this NP-complete problem is to find an assignment of packet transmission requests into a minimum number of time slots. A packet can be transmitted from one source to several destinations simultaneously by its replication. A time slot represents a switching configuration of the system with unit time for each packet transmission through an I/O line. The GNN consists of the binary neural network and the gradual expansion scheme. The binary neural network satisfies the constraints imposed on the system by solving the motion equation, whereas the gradual expansion scheme minimizes the number of required time slots by gradually expanding activated neurons. The performance is evaluated through simulations in practical size systems, where the GNN finds far better solutions than the best existing altorithm.

Narrow-band ISDN services may experience nonstationary traffic conditions. Therefore, switch design should take account of these conditions. We propose new performance measures for switching systems and describe a traffic model, which is a mixture of stationary Poissonian traffic and momentarily focused traffic. On the basis of this model, performance measures are determined so as to satisfy grade of service requirements that are in effect during some short interval after the momentarily focused traffic enters the system. We also propose an overload control scheme that uses these new performance measures. Finally, we show practical and numerical examples for the performance measures and overload control scheme.

Telecommunication services are becoming more and more personalized, integrated, and refined. Advanced personal and mobile telecommunication services, intelligent networks, and network management operations require cooperative network-wide distributed processing on a very large scale. Telecommunication programs must support these services with great flexibility, efficiency, and reliability. This paper proposes a new call processing model that improves the availability and flexibility of telecommunication programs. It first points out requirements, outlines the distributed processing platform PLATINA, and discusses several approaches to the enhanced call processing model. Then it explains the call processing program structure, and gives illustrations of mobile and multi- party service control as typical examples. The Caller-Callee decomposition reduces the complexity of the call processing program and enhances the call model; the separation of call and bearer enhances service flexibility and integration; distributed object-oriented techniques meet software evolution requirements. A prototype program has been implemented and has proved the effectiveness of this approach.

We propose a large capacity broadband packet switch architecture using multiple optical star couplers and tunable devices whose tuning range is restricted. The proposed switch has the conventional three-stage switch structure. With the use of the generalized knockout principle and tunable lasers arranged in an appropriate manner, the switch becomes an output queueing system that yields the best possible delay/throughput performance. This switch requires minimal hardware at the cost of the increased number of wavelengths.

Processors are important resources of stored program control (SPC) switching systems, and estimation of their workload level is crucial to maintaining service quality. Processor utilization is measured as processor usage per unit time, and workload level is usually estimated from measurement of this utilization during a given interval. This paper provides an approximate distribution of processor utilization of SPC switching systems, and it provides a method for designing an overload detection scheme. This method minimizes the observation interval required to keep overload detection errors below specified values. This observation interval is obtained as an optimal solution of a linear programming.

This paper describes a new method for designing switching software called DDL (Data Driven Logic). The new design method adopts the dataflow concept and graphical programming using a dataflow diagram. A dataflow diagram is used for software representation, and a dataflow mechanism is emulated on a conventional von Neumann processor. The DDL method has the following advantages; (1) general advantages of dataflow software; i.e. easily understandable programs using graphical representations, and easy description of parallelism, (2) modular design using reusable software components, (3) easy design and programming with a graphical user interface. This paper presents the general concepts and structure of DDL. It also discusses the dataflow emulation mechanism, the DDL software development process, the DDL programming environment, an evaluation of the DDL call processing program applied to a commercial PABX, and some unsolved problems of DDL.

Asynchronous Transfer Mode (ATM) switching system is expected to handle various kinds of media (such as motion video, computer data, and voice), and traffic control becomes essential to satisfy various quality requirements and to maintain efficient utilization of system resources. Priority control is one possible solution for realizing such a traffic control. In priority control, cells from various media are scheduled for transmission with different priority according to the quality class to which they belong. In this paper, we propose a new priority control method in which cells from various media are stored in their own buffer, we call it class buffer, and priority assignments are carried out based on the number of cells in each class buffer and the delay time. The number of cells in each class buffer is maintained using the counter circuit. The delay time of the cell is checked by the timer circuit for cell group, each of which consists of cells arriving during a periodical time interval. For simulation model, we consider three kinds of traffic; video, computer data, and voice, of which quality requirements are quite different. We show performance results in terms of the cell delay and the cell loss probability in our method through simulation.

This paper proposes a next-generation narrow-band ISDN (N-ISDN), including a suitable network and network node architecture. The proposed N-ISDN allows every subscriber to use H0/HI-class calls as easily as present telephone calls, and could rapidly expand ISDN services to all the subscribers of a public network. The present status of ISDN is first analyzed then the need for popularization of H0/HI-call services is discussed. The proposed key technologies to popularize HO/HI services are (1) on-chip integration of ISDN switching systems, (2) distribution of small on-chip switching systems over the subscriber switching area, (3) H0-based trunk circuit networks using H0 on-chip switching systems and (4) efficient and flexible call management for 64-kb/s basic-class calls. An estimation of hardware volume of switching nodes is used to show that the proposed architecture is more economical than other possible alternatives, i.e. conventional ISDN and B-ISDN.