Network service providers need to appropriately design systems and carefully configuring the settings and parameters to ensure that the systems keep running consistently and deliver the desired services. This can be a heavy and error-prone task. Intent-based system design methods have been developed to help with such tasks. These methods receive service-level requirements and generate service configurations to fulfill the given requirements. One such method is search-based system design, which can flexibly generate systems of various architectures. However, it has difficulty dealing with constraints on the quantitative parameters of systems, e.g., disk volume, RAM size, and QoS. To deal with practical cases, intent-based system design engines need to be able to handle quantitative parameters and constraints. In this work, we propose a new intent-based system design method based on search-based design that augments search states with quantitative constraints. Our method can generate a system that meets both functional and quantitative service requirements by combining a search-based design method with constraint checking. Experimental results show that our method can automatically generate a system that fulfills all given requirements within a reasonable computation time.

Spectrum sensing is one of the methods to identify available white spaces for secondary usage which was specified by the regulators. However, signal quality to be sensed can plunge to a very low signal-to-noise-ratio due to signal propagation and hence readings from individual sensors will be unreliable. Distributed sensing by the cooperation of multiple sensors is one way to cope with this problem because the diversity gain due to the combining effect of data captured at different position will assist in detecting signals that might otherwise not be detected by a single sensor. In effect, the probability of detection can be improved. We have implemented a distributed sensing system to evaluate the performance of different cooperative sensing algorithms. In this paper we describe our implementation and measurement experience which include the system design, specification of the system, measurement method, the issues and solutions. This paper also confirms the performance enhancement offered by distributed sensing algorithms, and describes several ideas for further enhancement of the sensing quality.

Product return is a critical but controversial issue. To deal with such a vague return problem, businesses must improve their information transparency in order to administrate the product return behaviour of their end users. This study proposes an intelligent return administration expert system (iRAES) to provide product return forecasting and decision support for returned product administration. The iRAES consists of two intelligent agents that adopt a hybrid data mining algorithm. The return diagnosis agent generates different alarms for certain types of product return, based on forecasts of the return possibility. The return recommender agent is implemented on the basis of case-based reasoning, and provides the return centre clerk with a recommendation for returned product administration. We present a 3C-iShop scenario to demonstrate the feasibility and efficiency of the iRAES architecture. Our experiments identify a particularly interesting return, for which iRAES generates a recommendation for returned product administration. On average, iRAES decreases the effort required to generate a recommendation by 70% compared to previous return administration systems, and improves performance via return decision support by 37%. iRAES is designed to accelerate product return administration, and improve the performance of product return knowledge management.

This paper describes a design of Ogg Vorbis decoder for embedded platform. Since Ogg Vorbis decoding process incurs high computational complexity, a trivial software-based implementation requires high operation frequency. Thus in our design specific hardware modules are devised for functional blocks, which have higher computational complexity than other blocks in Ogg Vorbis decoding process. Based on computational cost analysis of whole decoding process, IMDCT (Inverse Modified Discrete Cosine Transform) and residue decoding process are detected as the computation-intensive functional blocks. As a result of hardware implementation, 73% improvement in CPU load is achieved by specific hardware modules for IMDCT and residue decoding process.

The purpose of this paper is to present a rapid prototyping flow for the development of a wireless LAN system. The proposed system flow that was used for the development of the prototype is based on the use of UML (Unified Modeling Language). The UML and its real-time extensions are used to help the development phases of the prototype, mainly in the specification, co-simulation and validation of the design. The target of the development that was carried out with the application of the UML-based methodology is the implementation of an access point for a HIPERLAN/2 wireless network. Apart from the presentation of the UML-based system design methodology the paper also presents the application of the methodology for the implementation of the system prototype, the detailed software development and the results of the development.

The formulation of the process of analog system design has been done on the basis of the control theory application. This approach generalizes the design process and produces different design trajectories inside the same optimization procedure. The problem of the optimal design algorithm construction is defined as the minimal-time problem of the control theory. The main equations for the proposed design methodology were elaborated. These equations include the special control functions that are introduced artificially to generalize the design problem. Optimal dependencies of the control functions give the possibility to reduce the total computer design time. This idea was tested with different optimization algorithms of the design process. Numerical results of some simple electronic circuit design demonstrate the efficiency of the proposed approach. These examples show that the traditional design strategy is not time-optimal and the potential computer time gain of the optimal design strategy increases when the size and complexity of the system increase.

In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.

This paper proposes a methodology for fine evaluation of the uncertain behaviors of systems affected by any fluctuation of internal structures and internal parameters, by the use of a new concept on the fuzzy mapping. For a uniformly convex real Banach space X and Y, a fuzzy mapping G is introduced as the operator by which we can define a bounded closed compact fuzzy set G(x,y) for any (x,y)∈X×Y. An original system is represented by a completely continuous operator f defined on X, for instance, in a form xλ(f(x)) by a continuous operator λ: YX. The nondeterministic fluctuations induced into the original system are represented by a generalized form of the fuzzy mapping equation xGβ (x,f(x)) {ζX|µG(x,f(x))(ζ)β}, in order to give a fine evaluation of the solutions with respect to an arbitrarily–specified β–level. By establishing a useful fixed point theorem, the existence and evaluation problems of the "β–level-likely" solutions are discussed for this fuzzy mapping equaion. The theory developed here for the fluctuation problems is applied to the fine estimation of not only the uncertain behaviors of system–fluctuations but also the validity of system–models and -simulations with uncertain properties.

This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.