In this paper, the bit error rate (BER) considering tracking performance is evaluated, by theoretical analysis and computer simulation, for a bi-orthogonal system using a synchronizing pseudo-noise (PN) sequence and co-channel interference cancellers. A system that improves on Tachikawa's system is proposed. It is found that the optimum ratio of the information signal energy to the synchronizing signal energy varies with Eb/No, and the canceller is better for small L than for large L (L = length of the sequence). Moreover, it is found that the BER considering synchronization performance improvse as the equivalent noise bandwidth Bn decreases.

This paper presents a new method for the selftuning control of nonminimum phase discrete-time stochastic systems using approximate inverse systems obtained from the leastsquares approximation. Using this approximate inverse system the gain response of the system can be made approximately unit and phase response exactly zero. We show how unstable polezero cancellations can be avoided. This approximate inverse system can be used in the same manner for both minimum and nonminimum phase systems. Moreover, the degrees of the controller polynomials do not depend on the approximate inverse system. We just need an extra FIR filter in the feedforward path.

In this paper, a simple frame synchronization system for M-ary/SS communication systems is proposed, and synchronization performance and the resulting bit error rate performance are analyzed. The frame synchronization system uses racing counters and framing chips which are added to spreading sequences. M-ary/SS communication systems can improve bit error rate performance under the condition in which there is an additive white gaussian noise. Synchronization of M-ary/SS communication systems is difficult, however, because M-ary/SS communication systems have several spreading sequences. The authors proposed the simple frame synchronization system which uses only one chip in the spreading sequence as a framing signal. This system needs a long time for initial acquisition as the frame length is longer. The proposed system in this paper can make initial acquisition time short by increasing the number of framing chips. The proposed system corresponds to the conventional system when the number of framing chips is l. As the result, it is shown that several framing chips contribute to decrease the initial acquisition time. Moreover, the frame synchronization system can be applied to asynchronous M-ary/SSMA system when different framing chip pattern is assigned to each user.

In this paper, the bit error rate (BER) performance of the Spread Spectrum communication system with Constrained Spreading Codes (SS-CSC) is analyzed. The BER of the SS-CSC system is the same as that of the Bi-orthogonal system. Moreover, the frequency utilization efficiency of the SS-CSC system is better than that of the Bi-orthogonal system when K 10 and N = 3.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

This paper examines the performance of a direct sequence, spread spectrum (DSSS) multiple access (MA) system used over two typical, frequency-selective, fading satellite channels. In an attempt to increase the system efficiency, an adaptive receiver described by Rapajic and Vucetic [1] has been implemented. This system has been combined with soft-decision convolutional coding in order to improve the system performance under the fading conditions relative to the uncoded system and to allow as many simultaneous users as possible. Various code rates have been examined and the results are given. This paper specifically focuses on DSSS-MA systems with low spreading ratios. The satellite channels used in this paper were produced by models developed as a result of experimental measurements of fading satellite channels for rural and urban environments.

This paper proposes a novel Doppler frequency shift compensation technique to achieve terrestrial and low earth orbit (LEO) satellite dual mode DS/CDMA terminals robust to high Doppler shift and multipath fading. In order to satisfy the requirements of wide dynamic range and high accuracy simultaneously, the proposed scheme employs two stage compensation scheme, i.e., coarse compensation to keep dynamic range of about 100 kHz and fine compensation to satisfy its resolution of about 30 Hz, using block demodulation technique. Computer simulation results show that the proposed scheme can sufficiently compensate for the offset frequency up to the range of about 100 kHz at the terrestrial and LEO satellite combined mobile communication systems.

We present a topological framework of stepwise specification for concurrent systems in this paper. Some of description techniques can make topologies on the system space. Such topologies corresponds to abstract levels of those description techniques. Using a family of such description techniques, one can specify systems stepwisely. This framework allows to bridge various DTs and modularizing, so that global properties and module properties of systems become to be related to each other. Within this framework, we show derivation of a LOTOS cpecification from temporal logic formulae. An extended version of LOTOS with respect to concurrency is used in this paper. A semantics including concurrency is introduced to do this in this method. The method presented in this paper is applied to mobile telecommunication.

For high frequency video signals, display monitors for personal computers are required to shift from the horizontal scanning frequency fH=15.75 kHz for conventional TV broadcasting to fH=64 to 80 kHz, which is called XGA. Shifting to high frequencies and restrictions on the withstand voltage of horizontal transistors decrease the inductance of deflection yokes, which is an obstacle in manufacturing deflection yokes. A study was undertaken on an operation to permit deflection/high voltage integrated operation while keeping the inductance of the deflection yoke high. This paper reports the results.

This paper is devoted to a new design method for infinite impulse response approximate inverse system of a nonminimum phase system. The design is carried out such that the convolution of the nonminimum phase polynomial and its approximate inverse system can be represented by an approximately linear phase all-pass filter. A method for estimating the time delay and order of an approximate inverse system is also presented. Using infinite impulse response approximate inverse systems better accuracy is achieved with reduced computational complexity. Numerical examples are included to show the effectiveness of the proposed method.

This letter proposes a map-matching method for automotive navigation systems. The proposed method utilizes the innovation of the Kalman filter algorithm and can achieve more accurate positioning than the correlation method which is generally used for the navigation systems. In this letter, the performance of the proposed algorithm is verified by some simulations.

This paper concerns a Petri-net-based model for describing reactive and concurrent systems. Although many high-level Petri nets have been proposed, they are insufficiently practical to describe reactive and concurrent systems in the detail modeling, design and implementation phases. They are mainly intended to describe concurrent systems in the rough modeling phase and lack in several important features (e.g., concurrent tasks, task communication/synchronization, I/O interface, task scheduling) which the most actual implementations of reactive and concurrent systems have. Therefore it is impossible to simulate and analyze the systems accurately without explicitly modeling these features. On the other hand, programming languages based on Petri nets are deeply dependent on their execution environments and not sophisticated as modeling and specification languages. This paper proposes MENDEL net which is a high-level Petri net extended by incorporating concurrent tasks, task communication/synchronization, I/O interface, and task scheduling in a sophisticated manner. MENDEL nets are a wide-spectrum modeling language, that is, they are suitable for not only modeling but also designing and implementing reactive and concurrent systems.

In this paper, an extention for Haddad's method, which is the time-domain stability analysis on scalar nonlinear control systems, to multi-variable nonlinear control systems are proposed, and it is shown that these results are useful for the stability analysis of nonlinear control systems with various types of fuzzy controllers.

This paper proposed a fault localization and supervisory (SV) channel implementation for linear-repeaters (L-Reps) employing optical line amplifiers. In order to successfully introduce L-Reps into a Synchronous Digital Hierarchy (SDH)/Synchronous Optical Network (SONET)-based networks in a smooth, orderly fashion, layering of repeater section and supervisory system design must be taken into consideration. There supervisory techniques, such as linking analog-based and digital-based information, a precedence of digital-based information and an upstream precedence, for locating faulty L-Rep sections are proposed taking into consideration the difference in monitoring capabilities between L-Reps and regenerating-type repeaters (R-Reps). Furthermore, a linear repeater supervisory (LSV) channel configuration for L-Reps is also proposed. Finally, an SV system established in a prototype SDH-based 10-Gbit/s optical transmission system is briefly described.

The performance improvement of the partial response maximum-likelihood (PRML) system for (1, 7) run-length limited (RLL) code is studied. As a new PRML system, PR (1, 1, 0, 1, 1) system called modified E2PR4 (ME2PR4 ) followed by Viterbi detector for (1, 7) RLL code is proposed. At first, a determination method of the tap weights in transversal filter to equalize to PR (1, 1, 0, 1, 1) characteristic taking account of a noise correlation is described. And the equalization characteristics of the transversal filter are evaluated. Then, a Viterbi detector for ME2PR4 utilizing the constraint of run-length of (1, 7) RLL code is presented. Finally, the bit-error rate is obtained by computer simulation and the performance is compared with that of the conventional PRML systems called PR4, EPR4 and E2PR4 systems with Viterbi detector. The results show that among these systems our system exhibits the best performance and the SNR improvement increases with the increase in the linear density.

In the paper a new type of Multilayer Perceptron, developed in Quaternion Algebra, is adopted to realize short-time prediction of chaotic time series. The new introduced neural structure, based on MLP and developed in the hypercomplex quaternion algebra (HMLP) allows accurate results with a decreased network complexity with respect to the real MLP. The short term prediction of various chaotic circuits and systems has been performed, with particular emphasys to the Chua's circuit, the Saito's circuit with hyperchaotic behaviour and the Lorenz system. The accuracy of the prediction is evaluated through a correlation index between the actual predicted terms of the time series. A comparison of the performance obtained with both the real MLP and the hypercomplex one is also reported.

Electronic systems are progressively replacing mechanical devices or human operation for identifying people or objects in everyday-life applications. Especially, the contactless identification systems available today have several advantages, but they cannot handle easily several simultaneously present items. This paper describes a solution to this problem, based on blind source separation techniques. The effectiveness of this approach is experimentally demonstrated, especially by using a real-time DSP-based implementation of the proposed system.

We investigate bifurcations of the periodic solution observed in a phase converter circuit. The system equations can be considered as a nonlinear coupled system with Duffing's equation and an equation describing a parametric excitation circuit. In this system there are two types of solutions. One is with x = y = 0 which is the same as the solution of Duffing's equation (correspond to uncoupled case), another solution is with xy0. We obtain bifurcation sets of both solutions and discuss how does the coupling change the bifurcation structure. From numerical analysis we obtain a codimension two bifurcation which is intersection of double period-doubling bifurcations. Pericdic solutions generated by these bifurcations become chaotic states through a cascade of codimension three bifurcations which are intersections of D-type of branchings and period-doubling bifurcations.

In forthcoming multimedia environments, continuous-media data, such as video and audio data, will be used by a variety of multimedia applications. Multimedia applications require efficient and flexible support from real-time operating systems. This is because the changes in system and network loads require dynamic management of real-time thread behavior. If threads are implemented at the user level, operations on threads can be processed at the user level, and the efficient management of threads becomes possible by avoiding kernel interventions. Thus, we can provide an effective platform for multimedia applications. The goal of our work is to realize high-performance user-level real-time threads which satisfy the above requirements of multimedia systems. In this paper we describe the design and implementation of a user-level real-time threads package, called RTC-Threads, which is being developed on the RT-Mach microkernel. The results of performance evaluations show that our user-level real-time threads outperform real-time kernel-provided threads, which are implemented in the microkernel, in terms of efficiency and accuracy.

Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.