Wireless sensor networks represent a new data collection paradigm in which expandability plays an important role. In a practical monitoring environment, for example, food factory monitoring system, sensor relocations and reorganizations are necessary with reorganization of production lines and starting of new production lines. These relocations sometime make congestion in some area of the network. In this dynamic changing environment online expansion is a challenging problem for resource constraint network. This paper proposes a two-tier autonomous decentralized community architecture for wireless sensor network to solve the problem. The first layer consists of sensors and second layer consists of routers. In the architecture routers make community (a group of nodes mutually cooperate for a common goal is a community). The goal of this paper is to introduce the concept of sharing information among routers of the community to decrease sensor connection time for the network especially for the dynamic changing environment. Results show that our proposed technologies can reduce sensor connection time to achieve online expansion.

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.

Embedded systems are constrained by the available memory, and code-compression techniques address this issue by reducing the code size of application programs. The main challenge for the development of an effective code-compression technique is to reduce code size without affecting the overall system performance. Dictionary-based code-compression schemes are the most commonly used code-compression methods, because they can provide both good compression ratio and fast decompression. We propose an XOR-based reference scheme that can enhance the compression ratio on all the existing dictionary-based algorithms by changing the distribution of the symbols. Our approach works on all kinds of computer architecture with fixed length instructions, such as RISC or VLIW. Experiments show that our approach can further improve the compression ratio with nearly no hardware, performance, and power overheads.

Recent advances in cooperative communication and wireless Network Coding (NC) may lead to huge performance gains in relay systems. In this context, we focus on the two-way relay scenario, where two nodes exchange information via a common relay. We design a practical Superposition Coding (SC) based NC scheme for Decode-and-Forward (DF) half-duplex relaying, where the goal is to increase the achievable rate. By taking advantage of the direct link and by providing a suboptimal yet efficient power division among the superposed layers, our proposed SC two-way relaying scheme outperforms the reference schemes, including the well-known 3-step DF-NC scheme and the capacity of 2-step schemes for a large set of SNRs, while approaching closely the performance bound.

Both multiplexing and multi-user diversity are exploited based on Round Robin (RR) scheduling to achieve tradeoffs between average throughput and fairness in distributed antenna systems (DAS). Firstly, a parallel Round Robin (PRR) scheduling scheme is presented based on the multi-user multiplexing in spatial domain to enhance the throughput, which inherits the excellent fairness performance of RR. Then a parallel grouping Round Robin (PGRR) is proposed to exploit multi-user diversity based on PRR. Due to the integration of multi-user diversity and multi-user multiplexing, a great improvement of throughput is achieved in PGRR. However, the expense of the improvement is at the degradation of fairness since the "best channel criteria" is used in PGRR. Simulations verify analysis conclusions and show that tradeoffs between throughput and fairness can be achieved in PGRR.

To satisfy the requirement of a unified platform which can flexibly deal with various wireless radio systems, we proposed and implemented a heterogeneous network system composed of distributed flexible access points and a protocol-free signal processing unit. Distributed flexible access points are remote RF devices which perform the reception of multiple types of radio wave data and transfer the received data to the protocol-free signal processing unit through wired access network. The protocol-free signal processing unit performs multiple types of signal analysis by software. To realize a highly flexible and efficient radio wave data reception and transfer, we employ the recently developed compressed sensing technology. Moreover, we propose a combined Nyquist and compressed sampling method for the decoding signals to be sampled at the Nyquist rate and for the sensing signals to be sampled at the compressed rate. For this purpose, the decoding signals and the sensing signals are converted into the intermediate band frequency (IF) and mixed. In the IF band, the decoding signals are set at lower center frequencies than those of the sensing signals. The down converted signals are sampled at the rate of four times of the whole bandwidth of the decoding signals plus two times of the whole bandwidth of the sensing signals. The purpose of above setting is to simultaneously conduct Nyquist rate and compressed rate sampling in a single ADC. Then, all of odd (or even) samples are preserved and some of even (or odd) samples are randomly discarded. This method reduces the data transfer burden in dealing with the sensing signals while guaranteeing the realization of Nyquist-rate decoding performance. Simulation and experiment results validate the efficiency of the proposed method.

This letter proposes a novel censor-based scheme for cooperative spectrum sensing on Cognitive Radio Sensor Networks. A Takagi-Sugeno's fuzzy system is proposed to make the decision on the presence of the licensed user's signal based on the observed energy at each cognitive sensor node. The local spectrum sensing results are aggregated to make the final sensing decision at the fusion center after being censored to reduce transmission energy and reporting time. Simulation results show that significant improvement of the spectrum sensing accuracy, and saving energy as well as reporting time are achieved by our scheme.

We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.

Web APIs are offered in many Web sites for Ajax and mashup, but they have been developed independently since no reusable database component has been specifically created for Web applications. In this paper, we propose WAPDB, a distributed database management system for the rapid development of Web applications. WAPDB is designed on Atom, a set of Web API standards, and provides several of the key features required for Web applications, including efficient access control, an easy extension mechanism, and search and statistics capabilities. By introducing WAPDB, developers are freed from the need to implement these features as well as Web API processing. In addition, its design totally follows the REST architectural style, which gives uniformity and scalability to applications. We develop a proof-of-concept application with WAPDB, and find that it offers great cost effectiveness with no significant impact on performance; in our experiments, the development cost is reduced to less than half with the overhead (in use) of response times of just a few msec.

We address the issue of out-of-grammar (OOG) utterances in spoken dialogue systems by generating help messages. Help message generation for OOG utterances is a challenge because language understanding based on automatic speech recognition (ASR) of OOG utterances is usually erroneous; important words are often misrecognized or missing from such utterances. Our grammar verification method uses a weighted finite-state transducer, to accurately identify the grammar rule that the user intended to use for the utterance, even if important words are missing from the ASR results. We then use a ranking algorithm, RankBoost, to rank help message candidates in order of likely usefulness. Its features include the grammar verification results and the utterance history representing the user's experience.

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to soft errors, has not been taken into account in the conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor as a vulnerability measure for computer systems so that we evaluate task-wise reliability over various processor structures. Next we build a mixed integer linear programming (MILP) model for minimizing the chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

Multiple-input multiple-output (MIMO) repeater systems have been discussed in several published papers. When a repeater has only one antenna element, the propagation environment is called keyhole. In this kind of scenario the achievable channel capacity and link quality are decreased. Another limit is when the number of the antenna elements of a repeater is larger than that of a MIMO transceiver, the channel capacity cannot be increased. In this paper, in order to obtain an upper bound of the channel capacity, we express a propagation process of the distributed MIMO repeater system with amplify-and-forward method by the numerical formular, and optimize the position of each repeater.

In the field of software reengineering, many component identification approaches have been proposed for evolving legacy systems into component-based systems. Understanding the behaviors of various component identification approaches is the first important step to meaningfully employ them for legacy systems evolution, therefore we performed an empirical study on component identification technology with considerations of their similarity measures, clustering approaches and stopping criteria. We proposed a set of evaluation criteria and developed the tool CIETool to automate the process of component identification and evaluation. The experimental results revealed that many components of poor quality were produced by the employed component identification approaches; that is, many of the identified components were tightly coupled, weakly cohesive, or had inappropriate numbers of implementation classes and interface operations. Finally, we presented an analysis on the component identification approaches according to the proposed evaluation criteria, which suggested that the weaknesses of these clustering approaches were the major reasons that caused components of poor-quality.

Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks and limitations in the task allocation due to the accelerator-incompatible operations prevents us from gaining full potential of the heterogeneous multi-core processors. This paper presents a task allocation method based on algorithm transformation to increase the freedom of task allocation. We use approximation methods such as CORDIC algorithms to map the accelerator-incompatible operations to accelerator cores. According to the experimental results using HOG descriptor computation, the proposed task allocation method reduces the data transfer time by more than 82% and the total processing time by more than 79% compared to the conventional task allocation method.

This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

This paper addresses the coexistence issue of distributed heterogeneous networks where the network nodes are cognitive radio terminals. These nodes, operating as secondary users (SUs), might interfere with primary users (PUs) who are licensed to use a given frequency band. Further, due to the lack of coordination and the dissimilarity of the radio access technologies (RATs) among these wireless nodes, they might interfere with each other. To solve this coexistence problem, we propose an architecture that enables coordination among the distributed nodes. The architecture provides coexistence solutions and sends reconfiguration commands to SU networks. As an example, time sharing is considered as a solution. Further, the time slot allocation ratios and transmit powers are parameters encapsulated in the reconfiguration commands. The performance of the proposed scheme is evaluated in terms of the coexistence between PUs and SUs, as well as the coexistence among SUs. The former addresses the interference from SUs to PUs, whereas the latter addresses the sharing of an identified spectrum opportunity among heterogeneous SU networks for achieving an efficient spectrum usage. In this study, we first introduce a new parameter named as quality of coexistence (QoC), which is defined as the ratio between the quality of SU transmissions and the negative interference to PUs. In this study we assume that the SUs have multiple antennas and employ fixed transmit power control (fixed-TPC). By using the approximation to the distribution of a weighted sum of chi-square random variables (RVs), we develop an analytical model for the time slot allocation among SU networks. Using this analytical model, we obtain the optimal time slot allocation ratios as well as transmit powers of the SU networks by maximizing the QoC. This leads to an efficient spectrum usage among SUs and a minimized negative influence to the PUs. Results show that in a particular scenario the QoC can be increased by 30%.

Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to protect cryptography circuits from them. RSA is one of the most important cryptography algorithms because it effectively realizes a public-key cryptography system. RSA is extensively used but conventional scan-based side-channel attacks cannot be applied to it because it has a complicated algorithm. This paper proposes a scan-based side-channel attack which enables us to retrieve a secret key in an RSA circuit. The proposed method is based on detecting intermediate values calculated in an RSA circuit. We focus on a 1-bit time-sequence which is specific to some intermediate values. By monitoring the 1-bit time-sequence in the scan path, we can find out the register position specific to the intermediate value and we can know whether this intermediate value is calculated or not in the target RSA circuit. We can retrieve a secret key one-bit by one-bit from MSB to LSB. The experimental results demonstrate that a 1,024-bit secret key used in the target RSA circuit can be retrieved using 30.2 input messages within 98.3 seconds and its 2,048-bit secret key can be retrieved using 34.4 input within 634.0 seconds.

A Gaussian MIMO broadcast channel (GMBC) models the MIMO transmission of Gaussian signals from a transmitter to one or more receivers. Its capacity region and different precoding schemes for it have been well investigated, especially for the case wherein there are only transmit power constraints. In this paper, a special case of GMBC is investigated, wherein receive power constraints are also included. By imposing receive power constraints, the model, called protected GMBC (PGMBC), can be applied to certain scenarios in spatial spectrum sharing, secretive communications, mesh networks and base station cooperation. The sum capacity, capacity region, and application examples for the PGMBC are discussed in this paper. Sub-optimum precoding algorithms are also proposed for the PGMBC, where standard user precoding techniques are performed over a BC with a modified channel, which we refer to as the "protection-implied BC." In the protection-implied BC, the receiver protection constraints have been implied in the channel, which means that by satisfying the transmit power constraints on the protection implied channel, receiver protection constraints are guaranteed to be met. Any standard single-user or multi-user MIMO precoding scheme may then be performed on the protection-implied channel. When SINR-matching duality-based precoding is applied on the protection-implied channel, sum-capacity under full protection constraints (zero receive power), and near-sum-capacity under partial protection constraints (limited non-zero receive power) are achieved, and were verified by simulations.

Power-aware scheduling problem has been a recent issue in cluster systems not only for operational cost due to electricity cost, but also for system reliability. In this paper, we provide SLA-based scheduling algorithms for bag-of-tasks applications with deadline constraints on power-aware cluster systems. The scheduling objective is to minimize power consumption as long as the system provides the service levels of users. A bag-of-tasks application should finish all the sub-tasks before the deadline as the service level. We provide the power-aware scheduling algorithms for both time-shared and space-shared resource sharing policies. The simulation results show that the proposed algorithms reduce much power consumption compared to static voltage schemes.