This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

This paper proposes an adaptive resource allocation for multi-tier computing systems to guarantee a fair QoS level under resource constraints of tiers. We introduce a multi-tier computing architecture which consists of a group of resource managers and an arbiter. Resource allocation of each client is managed by a dedicated resource manager. Each resource manager updates resources allocated to subtasks of its client by locally exchanging QoS levels with other resource managers. An arbiter compensates the updated resources to avoid overload conditions in tiers. Based on the compensation by the arbiter, the subtasks of each client are executed in corresponding tiers. We derive sufficient conditions for the proposed resource allocation to achieve a fair QoS level avoiding overload conditions in all tiers with some assumptions on a QoS function and a resource consumption function of each client. We conduct a simulation to demonstrate that the proposed resource allocation can adaptively achieve a fair QoS level without causing any overload condition.

We describe a user scheduling scheme suitable for zero-forcing beamforming (ZFBF) downlink multiuser multiple-input multiple-output (MU-MIMO) orthogonal frequency-division multiplexing (OFDM) transmissions in time-division-duplex distributed antenna systems. This user scheduling scheme consists of inter-cell-interference mitigation scheduling by using fractional frequency reuse, proportional fair scheduling in the OFDM frequency domain, and high-capacity ZFBF-MU-MIMO scheduling by using zero-forcing with selection (ZFS). Simulation results demonstrate in a severe user-distribution condition that includes cell-edge users that the proposed user scheduling scheme achieves high average cell throughputs close to that provided by only ZFS and that it also achieves almost the same degree of user fairness as round-robin user scheduling.

This study examined the performance improvement of a photovoltaic (PV) array and inverter as well as their design, construction, and post-operation and management, which will become the key elements in future PV systems. In addition, it evaluated the performance characteristics of a 50 kW grid-connection PV system in Korea. According to the result of the evaluation, the PV array showed approximately 10% efficiency. The inverter was indicated to operate at > 90% efficiency regularly at > 400 W/m2 irradiation. The capture losses (Lc), system losses (Ls) and performance ratio were approximately 0.9 h/d, 0.3 h/d, and > 70%, respectively, indicating that the system was operating stably. In addition, while the Ls decreased rapidly due to the efficiency of the inverter, the performance ratio decreased markedly with increasing Lc due to the increase in temperature when the reference yield was > 5.0 h/d.

This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.

High efficiency power feeding systems are effective solutions for reducing the ICT power consumption with reducing power consumption of the ICT equipment and cooling systems. A higher voltage direct current (HVDC) power feeding system prototype was produced. This system is composed of a rectifier equipment, power distribution unit, batteries, and the ICT equipment. The configuration is similar to a -48 V DC power supply system. The output of the rectifier equipment is 100 kW, and the output voltage is 401.4 V. This paper present the configuration of the HVDC power feeding system and discuss its basic characteristics in the prototype system.

In this letter, we address the problem of downlink power allocation for the generalized distributed antenna system (DAS) with cooperative clusters. Considering practical applications, we assume that only the large-scale channel state information is available at the transmitter. The power allocation scheme is investigated with the target of ergodic achievable sum rate maximization. Based on some approximations and the Rayleigh Quotient Theory, the simple selective power allocation scheme is derived for the low SNR scenario and the high SNR scenario, respectively. The methods are applicable in practice due to their low complexity.

In a WSAN (Wireless Sensor and Actuator Network), most resources, including sensors and actuators, are designed for certain applications in a dedicated environment. Many researchers have proposed to use of gateways to infer and annotate heterogeneous data; however, such centralized methods produce a bottlenecking network and computation overhead on the gateways that causes longer response time in activity processing, worsening performance. This work proposes two distribution inference mechanisms: regionalized and sequential inference mechanisms to reduce the response time in activity processing. Finally, experimental results for the proposed inference mechanisms are presented, and it shows that our mechanisms outperform the traditional centralized inference mechanism.

Intrusion Detection Systems (IDS) have been received considerable attention among the network security researchers as one of the most promising countermeasures to defend our crucial computer systems or networks against attackers on the Internet. Over the past few years, many machine learning techniques have been applied to IDSs so as to improve their performance and to construct them with low cost and effort. Especially, unsupervised anomaly detection techniques have a significant advantage in their capability to identify unforeseen attacks, i.e., 0-day attacks, and to build intrusion detection models without any labeled (i.e., pre-classified) training data in an automated manner. In this paper, we conduct a set of experiments to evaluate and analyze performance of the major unsupervised anomaly detection techniques using real traffic data which are obtained at our honeypots deployed inside and outside of the campus network of Kyoto University, and using various evaluation criteria, i.e., performance evaluation by similarity measurements and the size of training data, overall performance, detection ability for unknown attacks, and time complexity. Our experimental results give some practical and useful guidelines to IDS researchers and operators, so that they can acquire insight to apply these techniques to the area of intrusion detection, and devise more effective intrusion detection models.

In real environments, the presence of ambient noise and room reverberations seriously degrades the accuracy in sound source localization. In addition, conventional sound source localization methods cannot localize multiple sound sources accurately in real noisy environments. This paper proposes a new method of multiple sound source localization using a distributed microphone system that is a recording system with multiple microphones dispersed to a wide area. The proposed method localizes a sound source by finding the position that maximizes the accumulated correlation coefficient between multiple channel pairs. After the estimation of the first sound source, a typical pattern of the accumulated correlation for a single sound source is subtracted from the observed distribution of the accumulated correlation. Subsequently, the second sound source is searched again. To evaluate the effectiveness of the proposed method, experiments of two sound source localization were carried out in an office room. The result shows that sound source localization accuracy is about 99.7%. The proposed method could realize the multiple sound source localization robustly and stably.

Interrupt service routines are a key technology for embedded systems. In this paper, we introduce the standard approach for using Generalized Stochastic Petri Nets (GSPNs) as a high-level model for generating CTMC Continuous-Time Markov Chains (CTMCs) and then use Markov Reward Models (MRMs) to compute the performance for embedded systems. This framework is employed to analyze two embedded controllers with low cost and high performance, ARM7 and Cortex-M3. Cortex-M3 is designed with a tail-chaining mechanism to improve the performance of ARM7 when a nested interrupt occurs on an embedded controller. The Platform Independent Petri net Editor 2 (PIPE2) tool is used to model and evaluate the controllers in terms of power consumption and interrupt overhead performance. Using numerical results, in spite of the power consumption or interrupt overhead, Cortex-M3 performs better than ARM7.

The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We realized many benchmark functions on the PBM128, and compared its memory size, computation time, and power consumption with the Intel's Core2Duo microprocessor. The PBM128 requires approximately a quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo. It dissipates a quarter of the power of the Core2Duo. Also, we realized packet filters such as an access controller and a firewall, and compared their performance with software on the Core2Duo. For these packet filters, the PBM128 requires approximately 17% of the memory for the Core2Duo, and is 21.3-23.7 times faster than the Core2Duo.

The proposed automated scoring system for English writing tests provides an assessment result including a score and diagnostic feedback to test-takers without human's efforts. The system analyzes an input sentence and detects errors related to spelling, syntax and content similarity. The scoring model has adopted one of the statistical approaches, a regression tree. A scoring model in general calculates a score based on the count and the types of automatically detected errors. Accordingly, a system with higher accuracy in detecting errors raises the accuracy in scoring a test. The accuracy of the system, however, cannot be fully guaranteed for several reasons, such as parsing failure, incompleteness of knowledge bases, and ambiguous nature of natural language. In this paper, we introduce an error-weighting technique, which is similar to term-weighting widely used in information retrieval. The error-weighting technique is applied to judge reliability of the errors detected by the system. The score calculated with the technique is proven to be more accurate than the score without it.

This paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.

In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

Due to the detachability of Flash storage, which is a dominant portable storage, data integrity stored in Flash storages becomes an important issue. This study considers the performance of Flash Translation Layer (FTL) schemes embedded in Flash storages in conjunction with file system behavior that pursue high data integrity. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In so doing, we quantify the performance of typical FTL schemes for a realistic digital camera workload that contains hot write references through experiments on a real system environment. Results show that for the workload with hot write references FTL performance does not conform with previously reported studies. We also conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

A scheme for designing a hierarchical fuzzy classification system with a different number of fuzzy partitions based on statistical characteristics of the data is proposed. To minimize the number of misclassified patterns in intermediate layers, a method of fuzzy partitioning from the defuzzified outputs of previous layers is also presented. The effectiveness of the proposed scheme is demonstrated by comparing the results from five datasets in the UCI Machine Learning Repository.

This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90 nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.

A digital spiking neuron is a wired system of shift registers that can generate spike-trains having various spike patterns by adjusting the wiring pattern between the registers. Inspired by the ultra-wideband impulse radio, a novel theoretical synthesis method of the neuron for application to spike-pattern division multiplex communications in an artificial pulse-coupled neural network is presented. Also, a novel heuristic learning algorithm of the neuron for realization of better communication performances is presented. In addition, fundamental comparisons to existing impulse radio sequence design methods are given.

The robust reduced order observer for a class of discrete-time Lipschitz nonlinear systems with external disturbance is proposed. It is shown that the proposed observer design can suppress the effect on the estimation error of external disturbance up to the prescribed level. Also, linear matrix inequalities are used to represent sufficient conditions on the existence of the proposed observer. Moreover, the maximum admissible Lipschitz constant of the proposed design is obtained for a given disturbance attenuation level. Finally, an illustrative example is given to verify the effectiveness of the proposed design.