A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Decreased power dissipation and transient voltage drops in CMOS power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits. In this paper, three CMOS buffers based on the charge-transfer, split-path and bootstrapped techniques to reduce the power dissipation and transient voltage drop in power supply are proposed. First, the inverted-delay-unit is used in the low-power inverted-delay-unit (LPID) CMOS buffer to eliminate the short-circuit current of the output stage. Second, the low-swing bootstrapped feedback-controlled split-path (LBFS) CMOS buffer is proposed to eliminate the short-circuit current of the output stage by using the feedback-controlled split-path method. The dynamic power dissipation of the LBFS CMOS buffer can be reduced by limiting the gate voltage swing of the output stage. Moreover, the propagation delay of the LBFS CMOS buffer is also reduced by non-full-swing gate voltage of the output stage. Third, the charge-recovery scheme is used in the charge-transfer feedback-controlled 4-split-path (CRFS) CMOS buffer to recovery and pull up the gate voltage of the output stage for reducing power-delay product and power line noise. Based on HSPICE simulation results, the power-delay product and the transient voltage drop in power supply of the proposed three CMOS buffers can be reduced by 20% to 40% as compared to conventional CMOS tapered buffer under various capacitive load.

None of the existing color constancy algorithms can be considered universal. Furthermore, they use all the image pixels, although actually not all of the pixels are effective in illumination estimation. Consequently, how to select a proper color constancy algorithm from existing algorithms and how to select effective(or useful) pixels from an image are two most important problems for natural images color constancy. In this paper, a novel Color Constancy method using Effective Regions (CCER) is proposed, which consists of the proper algorithm selection and effective regions selection. For a given image, the most proper algorithm is selected according to its Weilbull distribution while its effective regions are chosen based on image similarity. The experiments show promising results compared with the state-of-the-art methods.

Compressive sensing (CS) exploits the sparsity or compressibility of signals to recover themselves from a small set of nonadaptive, linear measurements. The number of measurements is much smaller than Nyquist-rate, thus signal recovery is achieved at relatively expense. Thus, many signal processing problems which do not require exact signal recovery have attracted considerable attention recently. In this paper, we establish a framework for parameter estimation of a signal corrupted by additive colored Gaussian noise (ACGN) based on compressive measurements. We also derive the Cramer-Rao lower bound (CRB) for the frequency estimation problems in compressive domain and prove some useful properties of the CRB under different compressive measurements. Finally, we show that the theoretical conclusions are along with experimental results.

Throughput capacity is of great importance for the design and performance optimization of mobile ad hoc networks (MANETs). We study the exact per node throughput capacity of MANETs under a general 2HR-(g, x, f) routing scheme which combines erasure coding and packet replication techniques. Under this scheme, a source node first encodes a group of g packets into x (x ≥ g) distinct coded packets, and then replicates each of the coded packets to at most f relay nodes which help to forward them to the destination node. All original packets can be recovered once the destination node receives any g distinct coded packets of the group. To study the throughput capacity, we first construct two absorbing Markov chain models to depict the complicated packet delivery process under the routing scheme. Based on these Markov models, an analytical expression of the throughput capacity is derived. Extensive simulation and numerical results are provided to verify the accuracy of theoretical results on throughput capacity and to illustrate how system parameters will affect the throughput capacity in MANETs. Interestingly, we find that the replication of coded packets can improve the throughput capacity when the parameter x is relatively small.

In this letter, high quality speech reconstruction approaches from Mel-frequency cepstral coefficients (MFCC) are presented. Taking into account of the nonnegative and sparse properties of the speech power spectrum, an alternating direction method of multipliers (ADMM) based nonnegative l2 norm (NL2) and weighted nonnegative l2 norm (NWL2) minimization approach is proposed to cope with the under-determined nature of the reconstruction problem. The phase spectrum is recovered by the well-known LSE-ISTFTM algorithm. Experimental results demonstrate that the NL2 and NWL2 approach substantially achieves better quality for reconstructed speech than the conventional l2 norm minimization approach, it sounds very close to the original speech when using the high-resolution MFCC, the PESQ score reaches 4.0.

Salient region detection is a fundamental problem in computer vision and image processing. Deep learning models perform better than traditional approaches but suffer from their huge parameters and slow speeds. To handle these problems, in this paper we propose the multi-feature fusion network (MFFN) - a efficient salient region detection architecture based on Convolution Neural Network (CNN). A novel feature extraction structure is designed to obtain feature maps from CNN. A fusion dense block is used to fuse all low-level and high-level feature maps to derive salient region results. MFFN is an end-to-end architecture which does not need any post-processing procedures. Experiments on the benchmark datasets demonstrate that MFFN achieves the state-of-the-art performance on salient region detection and requires much less parameters and computation time. Ablation experiments demonstrate the effectiveness of each module in MFFN.

In order to significantly reduce the time and space needed, compressive sensing builds upon the fundamental assumption of sparsity under a suitable discrete dictionary. However, in many signal processing applications there exists mismatch between the assumed and the true sparsity bases, so that the actual representative coefficients do not lie on the finite grid discretized by the assumed dictionary. Unlike previous work this paper introduces the unified compressive measurement operator into atomic norm denoising and investigates the problems of recovering the frequency support of a combination of multiple sinusoids from sub-Nyquist samples. We provide some useful properties to ensure the optimality of the unified framework via semidefinite programming (SDP). We also provide a sufficient condition to guarantee the uniqueness of the optimizer with high probability. Theoretical results demonstrate the proposed method can locate the nonzero coefficients on an infinitely dense grid over a wide range of SNR case.

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 µm CMOS technology, and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 µW at 304 MHz.

In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset (SEU), i.e. particle striking induced logic upset, regardless of the energy of the striking particle. The proposed robust latch offers a much wider spectrum of working clock frequency on account of a smaller delay and insensitivity to high impedance state. The proposed robust latch performs with lower costs regarding power and area than most of the compared latches. SPICE simulation results demonstrate that the area-power-delay product is 73.74% saving on average compared with previous radiation hardened latches.

Three-dimensional integrated circuits (3D ICs) that employ through-silicon vias (TSVs) integrating multiple dies vertically have opened up the potential of highly improved circuit designs. However, various types of TSV defects may occur during the assembly process, especially the clustered TSV faults because of the winding level of thinned wafer, the surface roughness and cleanness of silicon dies,inducing TSV yield reduction greatly. To tackle this fault clustering problem, router-based and ring-based TSV redundancy architectures were previously proposed. However, these schemes either require too much area overhead or have limited reparability to tolerant clustered TSV faults. Furthermore, the repairing lengths of these schemes are too long to be ignored, leading to additional delay overhead, which may cause timing violation. In this paper, we propose a region-based TSV redundancy design to achieve relatively high reparability as well as low additional delay overhead. Simulation results show that for a given number of TSVs (8*8) and TSV failure rate (1%), our design achieves 11.27% and 20.79% reduction of delay overhead as compared with router-based design and ring-based scheme, respectively. In addition, the reparability of our proposed scheme is much better than ring-based design by 30.84%, while it is close to that of the router-based scheme. More importantly, the overall TSV yield of our design achieves 99.88%, which is slightly higher than that of both router-based method (99.53%) and ring-based design (99.00%).

This letter presents a speech watermarking scheme that is combined with CELP (Code Excited Linear Prediction) speech coding for speech authentication. The excitation codebook of CELP is partitioned into three parts and labeled '0', '1' and 'any' according to the private key. Watermark embedding process chooses the codebook whose label is the same as the watermark bit and combines it with the codebook labeled 'any' for CELP coding. A statistical method is employed to detect the watermark, and the watermark length for authentication and detection threshold are determined by false alarm probability and missed detection probability. The new codebook partition technique produces less distortion, and the statistical detection method guarantees that the error probability can be controlled under prescribed level.

The rapid development of information techniques has lead to more and more high-dimensional datasets, making classification more difficult. However, not all of the features are useful for classification, and some of these features may even cause low classification accuracy. Feature selection is a useful technique, which aims to reduce the dimensionality of datasets, for solving classification problems. In this paper, we propose a modified bat algorithm (BA) for feature selection, called MBAFS, using a SVM. Some mechanisms are designed for avoiding the premature convergence. On the one hand, in order to maintain the diversity of bats, they are guided by the combination of a random bat and the global best bat. On the other hand, to enhance the ability of escaping from local optimization, MBAFS employs one mutation mechanism while the algorithm trapped into local optima. Furthermore, the performance of MBAFS was tested on twelve benchmark datasets, and was compared with other BA based algorithms and some well-known BPSO based algorithms. Experimental results indicated that the proposed algorithm outperforms than other methods. Also, the comparison details showed that MBAFS is competitive in terms of computational time.

Saliency detection is widely used in many vision tasks like image retrieval, compression and person re-identification. The deep-learning methods have got great results but most of them focused more on the performance ignored the efficiency of models, which were hard to transplant into other applications. So how to design a efficient model has became the main problem. In this letter, we propose parallel feature network, a saliency model which is built on convolution neural network (CNN) by a parallel method. Parallel dilation blocks are first used to extract features from different layers of CNN, then a parallel upsampling structure is adopted to upsample feature maps. Finally saliency maps are obtained by fusing summations and concatenations of feature maps. Our final model built on VGG-16 is much smaller and faster than existing saliency models and also achieves state-of-the-art performance.

With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.

As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs. We reveal for the first time that production defects in such hardened latches can cause two serious problems: (1) these production defects are difficult to detect with conventional scan test and (2) these production defects can reduce the reliability of hardened latches. This paper systematically addresses these two problems with three major contributions: (1) Post-Test Vulnerability Factor (PTVF), a first-of-its-kind metric for quantifying the impact of production defects on hardened latches, (2) a novel Scan-Test-Aware Hardened Latch (STAHL) design that has the highest defect coverage compared to state-of-the-art hardened latch designs, and (3) an STAHL-based scan test procedure. Comprehensive simulation results demonstrate the accuracy of the proposed PTVF metric and the effectiveness of the STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs for safety-critical applications.

In a shared buffer packet switch, a good buffer management scheme is needed to reduce the overall packet loss probability and improve the fairness between different users. In this paper, a novel buffer control scheme called partial sharing and partial partitioning (PSPP) is proposed. The PSPP is an adaptive scheme that can be dynamically adjusted to the changing traffic conditions while simple to implement. The key idea of the PSPP is that part of the buffer space, proportional to the number of inactive output ports, is reserved for sharing between inactive output ports. This portion of buffer is called PS buffer. The residual buffer space, called PP buffer, is partitioned and distributed to active output ports equally. From the analysis results, we only need to reserve a small amount of PS buffer space to get good performance for the entire system. Computer simulation shows the PSPP control is very robust and very close to the performance of pushout (PO) buffer management scheme which is a scheme considered as optimal in terms of fairness and total loss ratio while too complicated for implementation.

Compared with acoustic microphone (AM) speech, bone-conducted microphone (BCM) speech is much immune to background noise, but suffers from severe loss of information due to the characteristics of the human-body transmission channel. In this letter, a new method for the speaker-dependent BCM speech enhancement is proposed, in which we focus our attention on the spectra restoration of the distorted speech. In order to better infer the missing components, an attention-based bidirectional Long Short-Term Memory (AB-BLSTM) is designed to optimize the use of contextual information to model the relationship between the spectra of BCM speech and its corresponding clean AM speech. Meanwhile, a structural error metric, Structural SIMilarity (SSIM) metric, originated from image processing is proposed to be the loss function, which provides the constraint of the spectro-temporal structures in recovering of the spectra. Experiments demonstrate that compared with approaches based on conventional DNN and mean square error (MSE), the proposed method can better recover the missing phonemes and obtain spectra with spectro-temporal structure more similar to the target one, which leads to great improvement on objective metrics.