This paper proposes a compact, low-power, and rail-to-rail class-B output buffer for driving the large column line capacitance of LCDs. The comparator used as a nonlinear element in feedback path is modified from the current-mirror amplifier, which has area and power advantages. The output buffer was realized in a 0.35 m CMOS process. The active area of the buffer is 8673.5 m2. With a 3.3 V supply, the measured quiescent current is 7.4 A. The settling time for 0.05-3.25 V swing to within 0.2% is 8 s.

This paper describes the design and results of low cost integrated CMOS local and remote temperature sensors with digital outputs. No trimming is needed to obtain good temperature linearity, so that only one-temperature calibration is needed which greatly reduces testing cost. The base-emitter voltage of the parasitic substrate bipolar transistor is used to measure the local temperature. A diode-connected external bipolar transistor is used to measure the remote temperature. Chopper techniques were used to cancel the offset voltage of the op-amp, so that a precise bandgap voltage can be obtained without resistance trimming. A first order ΣΔ ADC was used to produce the digital output. The local and remote temperature sensors were realized in a 0.6 µm single-poly triple-metal CMOS technology with active area of 0.6 mm2 and 0.65 mm2, respectively. After calibration, the error is 1 for the local temperature sensor over the temperature range of -20 to 130, and 2 for the remote temperature sensor over the range of 0 to 120. The supply currents of the local and remote temperature sensors are 3.5 µA and 38 µA at 8 samples/s, respectively.

Direction of arrival (DOA) estimation as a fundamental issue in array signal processing has been extensively studied for many applications in military and civilian fields. Many DOA estimation algorithms have been developed for different application scenarios such as low signal-to-noise ratio (SNR), limited snapshots, etc. However, there are still some practical problems that make DOA estimation very difficult. One of them is the correlation between sources. In this paper, we develop a sparsity-based method to estimate the DOA of coherent signals with sparse linear array (SLA). We adopt the off-grid signal model and solve the DOA estimation problem in the sparse Bayesian learning (SBL) framework. By considering the SLA as a ‘missing sensor’ ULA, our proposed method treats the output of the SLA as a partial output of the corresponding virtual uniform linear array (ULA) to make full use of the expanded aperture character of the SLA. Then we employ the expectation-maximization (EM) method to update the hyper-parameters and the output of the virtual ULA in an iterative manner. Numerical results demonstrate that the proposed method has a better performance in correlated signal scenarios than the reference methods in comparison, confirming the advantage of exploiting the extended aperture feature of the SLA.

A robust adaptive beamforming algorithm is proposed based on the precise interference-plus-noise covariance matrix reconstruction and steering vector estimation of the desired signal, even existing large gain-phase errors. Firstly, the model of array mismatches is proposed with the first-order Taylor series expansion. Then, an iterative method is designed to jointly estimate calibration coefficients and steering vectors of the desired signal and interferences. Next, the powers of interferences and noise are estimated by solving a quadratic optimization question with the derived closed-form solution. At last, the actual interference-plus-noise covariance matrix can be reconstructed as a weighted sum of the steering vectors and the corresponding powers. Simulation results demonstrate the effectiveness and advancement of the proposed method.

A workflow may be extended to adapt to market growth, legal reform, and so on. The extended workflow must be logically correct, and inherit the behavior of the existing workflow. Even if the extended workflow inherits the behavior, it may be not logically correct. Can we modify it so that it satisfies not only behavioral inheritance but also logical correctness? This is named behavioral inheritance preserving soundizability problem. There are two kinds of behavioral inheritance: protocol inheritance and projection inheritance. In this paper, we tackled protocol inheritance preserving soundizability problem using a subclass of Petri nets called workflow nets. Limiting our analysis to acyclic free choice workflow nets, we formalized the problem. And we gave a necessary and sufficient condition on the problem, which is the existence of a key structure of free choice workflow nets called TP-handle. Based on this condition, we also constructed a polynomial time procedure to solve the problem.

In this paper, a novel technique using proportional current feedback is proposed to improve dynamic response of digital PWM DC-DC converters. Generally, digital controllers are implemented using microprocessors or DSPs. Additional A/D converters are required to sense feedback signals. Proposed simple structure makes it feasible to integrate both A/D converter and digital controller on a single chip. System complexity and hardware cost are therefore greatly reduced. A behavioral time domain circuit model is proposed and analyzed using MATLAB. Both simulation and experimental results showed satisfactory performance to meet power requirements of microprocessors.

This paper describes the robust design of the 30 V high voltage NMOS (HVNMOS) structure implemented in a 0.6 µm 5 V standard CMOS processes without any additional masks or process steps. The structure makes use of the field oxide (FOX) and light doping N-well to increase the drain to gate and drain to bulk breakdown voltages, respectively. By varying the six spacing parameters: the channel length, gate overlap FOX, N-well overlap channel length, poly to the active area of the drain (OD2), metal extend beyond the OD2 and N-well extend beyond the OD2 in HVNMOS structure, the breakdown voltage can be improved. The experimental results show that the breakdown voltage of the normal NMOS is 11 V, and the breakdown voltage of the HVNMOS is increased to over 30 V. With the optimized layout parameters of the HVNMOS, it can be increased to 38 V.

A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m 714 µ m.

This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318 MHz. The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spectrum digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 µm single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826396 µm2 and 790298 µm2, respectively. The total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.

In this letter we present efficient iterative frequency domain equalization for single-carrier (SC) transmission systems with insufficient cyclic prefix (CP). Based on minimum mean square error (MMSE) criteria, iterative decision feedback frequency domain equalization (IDF-FDE) combined with cyclic prefix reconstruction (CPR) is derived to mitigate inter-symbol interference (ISI) and inter-carrier interference (ICI). Computer simulation results reveal that the proposed scheme significantly improves the performance of SC systems with insufficient CP compared with previous schemes.

To increase the number of the embedded secrets and to improve the quality of the stego-image in the vector quantization (VQ)-based information hiding scheme, in this paper, we present a novel information-hiding scheme to embed secrets into the side match vector quantization (SMVQ) compressed code. First, a host image is partitioned into non-overlapping blocks. For these seed blocks of the image, VQ is adopted without hiding secrets. Then, for each of the residual blocks, SMVQ or VQ is employed according to the smoothness of the block such that the proper codeword is chosen from the state codebook or the original codebook to compress it. Finally, these compressed codes represent not only the host image but also the secret data. Experimental results show that the performance of the proposed scheme is better than other VQ-based information hiding scheme in terms of the embedding capacity and the image quality. Moreover, in the proposed scheme, the compression rate is better than the compared scheme.

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.

The major application of digital data hiding techniques is to deliver confidential data secretly via public but unreliable computer networks. Most of the existing data hiding schemes, however, exploit the raw data of cover images to perform secret communications. In this paper, a novel data hiding scheme was presented with the manipulation of images based on the compression of side-match vector quantization (SMVQ). This proposed scheme provided adaptive alternatives for modulating the quantized indices in the compressed domain so that a considerable quantity of secret data could be artfully embedded. As the experimental results demonstrated, the proposed scheme indeed provided a larger payload capacity without making noticeable distortions in comparison with schemes proposed in earlier works. Furthermore, this scheme also presented a satisfactory compression performance.

A lithium-ion (Li-ion) battery protection IC with an average current of 0.99 µA (at a battery voltage of 3.6 V) and a standby current (after detecting over-discharge) less than 0.01 µA is presented. This low power performance is achieved via a power-on duty-cycle technique. The protection circuit samples the voltage of the battery periodically and powers down during the rest of time. This Li-ion battery protector provides over-charge, over-discharge, excess-current and short circuits protection. This protection IC was implemented in a 0.6-µm CMOS technology and the active area is 880 µm 780 µm.

A new method for adaptive digital beamforming technique with compressed sensing (CS) for sparse receiving arrays with gain/phase uncertainties is presented. Because of the sparsity of the arriving signals, CS theory can be adopted to sample and recover receiving signals with less data. But due to the existence of the gain/phase uncertainties, the sparse representation of the signal is not optimal. In order to eliminating the influence of the gain/phase uncertainties to the sparse representation, most present study focus on calibrating the gain/phase uncertainties first. To overcome the effect of the gain/phase uncertainties, a new dictionary optimization method based on the total least squares (TLS) algorithm is proposed in this paper. We transfer the array signal receiving model with the gain/phase uncertainties into an EIV model, treating the gain/phase uncertainties effect as an additive error matrix. The method we proposed in this paper reconstructs the data by estimating the sparse coefficients using CS signal reconstruction algorithm and using TLS method toupdate error matrix with gain/phase uncertainties. Simulation results show that the sparse regularized total least squares algorithm can recover the receiving signals better with the effect of gain/phase uncertainties. Then adaptive digital beamforming algorithms are adopted to form antenna beam using the recovered data.

A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64 mA current @ VOL/VOH = 0.4 V/4.6 V, with 66 pF and 50 Ω loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 µm CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.