In this paper, we have investigated the characteristics of PdYb-silicide layer formed by the silicidation of Pd/Yb/n-Si(100) stacked structures for the first time. Pd (12-20 nm)/Yb (0-8 nm) stacked layers were deposited on n-Si(100) substrates by the RF magnetron sputtering at room temperature. Then, 10 nm-thick HfN encapsulating layer was deposited at room temperature. Next, silicidation was carried out by the RTA at 500°C/1 min in N2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, Schottky barrier height (SBH) for electron was reduced from 0.73 eV of Pd2Si to 0.4 eV of PdYb-silicide in case the Pd/Yb thicknesses were 14/6 nm, respectively.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

In this research, we investigated the metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5nm thick nondoped HfO2 gate insulator by decreasing the sputtering power for Pt gate electrode deposition. The leakage current was effectively reduced to 2.6×10-8A/cm2 at the voltage of -1.5V by the sputtering power of 40W for Pt electrode deposition. Furthermore, the memory window (MW) of 0.53V and retention time over 10 years were realized.

We have investigated PtHf silicide formation utilizing a developed PtHf-alloy target to realize low contact resistivity for the first time. A 20 nm-thick PtHf-alloy thin film was deposited on the n-Si(100) by RF magnetron sputtering at room temperature. Then, silicidation was carried out by rapid thermal annealing (RTA) system at 450-600°C/5 min in N2/4.9%H2 ambient. The PtHf-alloy silcide, PtHfSi, layers were successfully formed, and the Schottky barrier height (SBH) for electron of 0.45 eV was obtained by 450°C silicidation. Furthermore, low contact resistivity was achieved for fabricated PtHSi such as 8.4x10-8 Ωcm2 evaluated by cross-bridge Kelvin resistor (CBKR) method.

In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9 eV) and Yb (2.7 eV). Pt (10-20 nm)/Hf, Yb (0-10 nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of PtxHf1 - xSi formed at 400/60 min annealing in N2, SBH for electron was reduced from 0.85 eV to 0.53 eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

In this study, we investigated Si(100), Si(110) and Si(111) surface flattening process utilizing sacrificial oxidation method, and its effect on Metal-Insulator-Semiconductor (MIS) diode characteristics. By the etching of the 100 nm-thick sacrificial oxide formed by thermal oxidation at 1100°C, the surface roughness of Si(100), Si(110) and Si(111) substrates were reduced. The obtained Root-Mean-Square (RMS) roughness of Si(100) was reduced from 0.22 nm (as-cleaned) to 0.07 nm (after etching), while it was reduced from 0.23 nm to 0.12 nm in the case of Si(110), and from 0.23 nm to 0.11 nm in the case of Si(111), respectively. Furthermore, it was found that time-dependent dielectric breakdown (TDDB) characteristics of MIS diodes for p-Si(100), p-Si(110) and p-Si(111) were improved with the reduction of Si surface RMS roughness.

In this study, Si(100) surface flattening process was investigated utilizing sacrificial oxidation method to improve Metal--Insulator--Semiconductor (MIS) diode characteristics. By etching of the 100,nm-thick sacrificial oxide formed by thermal oxidation at 1100$^{circ}$C, the surface roughness of Si substrate was reduced. The obtained Root-Mean-Square (RMS) roughness was decreased from 0.15,nm (as-cleaned) to 0.07,nm in the case of sacrificial oxide formed by wet oxidation, while it was 0.10,nm in the case of dry oxidation. Furthermore, time-dependent dielectric breakdown (TDDB) characteristic of Al/SiO$_{2}$(10,nm)/p-Si(100) MIS diode structures was found to be improved by the reduction of Si surface RMS roughness.

In this research, we have investigated the deposition condition of pentacene film on nitrogen doped (N-doped) LaB6 donor layer for larger grain growth at the channel region for bottom-contact type pentacene-based organic field-effect transistors (OFETs) to improve the device characteristics. Source and drain bottom-contacts of Al were patterned and 2nm-thick N-doped LaB6 donor layer was deposited on the SiO2/Si(100) back-gate structure. The dendritic grain growth of pentacene larger than 10µm without lamellar grain growth was demonstrated when the deposition temperature and rate were 100°C and 0.5nm/min, respectively. Furthermore, it was found that the dendritic grain growth was realized at the boundary region of bottom-contact as well as channel region.

Twin-Channel (TC)-MOSFET with twin omega-gate (Ω-gate) Si channels and its fabrication process were proposed. The twin Si channels are able to be fabricated by self-aligned process utilizing wet etching of SiN and silicon-on-insulator (SOI) wafers. Three-dimensional (3-D) device simulation was performed to optimize gate structure for TC-MOSFET with 10 nm10 nm (TSiWG) channels with the gate length of 30 nm, and it was found that TC-MOSFET with right-angled Ω-gate in case the Lunder was 3 nm showed excellent device characteristics similar to the gate-all-around (GAA) devices corresponding to the gate structure as Lunder=5 nm. Fabrication process of twin Si channels was also investigated experimentally, and approximately 40 nm40 nm twin Si channels were successfully fabricated on SOI by the proposed fabrication process.

Ferroelectric gate field-effect transistors (MFSFETs) were investigated utilizing nondoped HfO2 deposited by RF magnetron sputtering utilizing Hf target. After the post-metallization annealing (PMA) process with Pt top gate at 500°C/30s, ferroelectric characteristic of 10nm thick nondoped HfO2 was obtained. The fabricated MFSFETs showed the memory window of 1.7V when the voltage sweep range was from -3 to 3V.

In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (Dit) on the order of 1011eV-1cm-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

We have investigated the in-situ N2-plasma nitridation for high-k HfN gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering to improve the electrical characteristics. It was found that the increase of nitridation gas pressure for the deposited HfN1.1 gate insulator, such as 98 mPa, decreased both the hysteresis width in C-V characteristics and leakage current. Furthermore, the 2-step nitiridation process with the nitridation gas pressure of 26 mPa followed by the nitridation at 98 mPa realized the decrease of equivalent oxide thickness (EOT) to 0.9 nm with decreasing the hysteresis width and leakage current. The fabricated metal-insulator-semiconductor field-effect transistor (MISFET) with 2-step nitridation showed a steep subthreshold swing of 87 mV/dec.

We investigated the low temperature formation of Pd2Si on Si(100) with TiN encapsulating layer formed at 500°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x1015 cm-2 for B+. The uniform Pd2Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500°C. The estimated Schottky barrier height to hole of 0.20 eV (qφBp) was realized for n-Si(100).

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.