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38801-38820hit(42756hit)

  • Definition of Attributed Random Graph and Proposal of Its Applications

    Dong Su SEONG  Ho Sung KIM  Kyu Ho PARK  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E76-D No:8
      Page(s):
    919-925

    In this paper, we define an attributed random graph, which can be considered as a generalization of conventional ones, to include multiple attributes as well as numeric attribute instead of a single nominal attribute in random vertices and edges. Then we derive the probability equations for an attributed graph to be an outcome graph of the attributed random graph, and the equations for the entropy calculation of the attributed random graph. Finally, we propose the application areas to computer vision and machine learning using these concepts.

  • A Network-Topology-Independent Static Task Allocation Strategy for Massively Parallel Computers

    Takanobu BABA  Akehito GUNJI  Yoshifumi IWAMOTO  

     
    PAPER-Computer Networks

      Vol:
    E76-D No:8
      Page(s):
    870-881

    A network-topology-independent static task allocation strategy has been designed and implemented for massively parallel computers. For mapping a task graph to a processor graph, this strategy evaluates several functions that represent some intuitively feasible properties or the graphs. They include the connectivity with the allocated nodes, distance from the median of a graph, connectivity with candidate nodes, and the number of candidate nodes within a distance. Several greedy strategies are defined to guide the mapping process, utilizing the indicated function values. An allocation system has been designed and implemented based on the allocation strategy. In experiments we have defined about 1000 nodes in task graphs with regular and irregular topologies, and the same order of processors with mesh, tree, and hypercube topologies. The results are summarized as follows. 1) The system can yield 4.0 times better total communication costs than an arbitrary allocation. 2) It is difficult to select a single strategy capable of providing the best solutions for a wide range of task-processor combinations. 3) Comparison with hypercube-topology-dependent research indicates that our topology-independent allocator produces better results than the dependent ones. 4) The order of computaion time of the allocator is experimentally proved to be O (n2) where n represents the number of tasks.

  • A Modular Inversion Hardware Algorithm with a Redundant Binary Representation

    Naofumi TAKAGI  

     
    PAPER-Computer Hardware and Design

      Vol:
    E76-D No:8
      Page(s):
    863-869

    A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set {0, 1,1}. All addition/subtractions are performed without carry propagation. A modular inversion is carried out in O (n) clock cycles where n is the word length of the modulus. The length of each clock cycle is constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.

  • Fabrication and Characterization of Bi-epitaxial Grain Boundary Junctions in YBa2Cu3O7δ

    Kazuya KINOSHITA  Syuuji ARISAKA  Takeshi KOBAYASHI  

     
    PAPER

      Vol:
    E76-C No:8
      Page(s):
    1265-1270

    We have fabricated bi-epitaxial grain boundary junctions in YBa2Cu3O7δ (YBCO) thin films by using SrTiO3 (STO) seed layers on MgO(100) substrate. YBCO film growing over the STO seed layer has a different in-plane orientation from YBCO film without the seed layer, so artificial grain boundaries were created at the edge of the seed layer. The fabricated junctions have high Tc (up to 80 K), and constant-voltage current steps are observed in response to 12.1 GHz microwave radiation. Moreover, some of the junctions show characteristic current-voltage curves comprising not only an usual Josephson-like characteristic but also a low critical current due to the flux creep. This suggests that the two characteristic parts are likely to be connected in series at the junction region.

  • The Comparison between the Linear Optimal Restoration Filter and MEM Restoration Filter

    Kiyomichi ARAKI  Toshihiko HASHIMOTO  

     
    LETTER-Digital Image Processing

      Vol:
    E76-A No:8
      Page(s):
    1353-1355

    In this paper, we attempt the comparison of the image/signal restoration between Projection Filter, which is regarded as one of the linear optimal filters, and the non-linear filter based on MEM. From the simulation, we show the advantage of MEM restoration filter in restoring noisy degraded images.

  • Linearization Analysis of Threshold Characteristics for Some Applications of Mutually Coupled SQUIDs

    Yoshinao MIZUGAKI  Koji NAKAJIMA  Tsutomu YAMASHITA  

     
    PAPER

      Vol:
    E76-C No:8
      Page(s):
    1291-1297

    The threshold characteristics of mutually coupled SQUIDs (Superconducting Quantum Interference Devices) have been analytically and numerically investigated. The mutually coupled SQUIDs investigated is composed of an rf-SQUID and a dc-SQUID. Here, the rf-SQUID is a flux quantum generator and the dc-SQUID is a flux detector. The linearization method substituting sin-1x by (π/2)x (1x1) is found valid when it is applied to the mutually coupled SQUIDs, because it is possible to obtain the superconducting regions analytically. By computer implementation of linearization method, we found this method is very effective and very quick compared to the ordinary methods. We report the internal flux on an rf-SQUID, the threshold of a dc-SQUID, and that of mutually coupled SQUIDs obtained by Lagrange multiplier formulation and linearization. The features of the threshold characteristics of the mutually coupled SQUIDs with various parameters are also reported. The discontinuous behavior of threshold of the mutually coupled SQUIDs are attractive for digital applications. We suggest three applications of the mutually coupled SQUIDs, that is, a logic gate for high-Tc superconductors (HTSs), a neuron device, and an A/D converter.

  • An Adaptive Sensing System with Tracking and Zooming a Moving Object

    Junghyun HWANG  Yoshiteru OOI  Shinji OZAWA  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E76-D No:8
      Page(s):
    926-934

    This paper describes an adaptive sensing system with tracking and zooming a moving object in the stable environment. Both the close contour matching technique and the effective determination of zoom ratio by fuzzy control are proposed for achieving the sensing system. First, the estimation of object feature parameters, 2-dimensional velocity and size, is based on close contour matching. The correspondence problem is solved with cross-correlation in projections extracted from object contours in the specialized difference images. In the stable environment, these contours matching, capable of eliminating occluded contours or random noises as well as background, works well without heavy-cost optical flow calculation. Next, in order to zoom the tracked object in accordance with the state of its shape or movement practically, fuzzy control is approached first. Three sets of input membership function--the confidence of object shape, the variance of object velocity, and the object size--are evaluated with the simplified implementation. The optimal focal length is achieved of not only desired size but safe tracking in combination with fuzzy rule matrix constituted of membership functions. Experimental results show that the proposed system is robust and valid for numerous kind of moving object in real scene with system period 1.85 sec.

  • Implementation of an Industrial R/C System Using a Hybrid DS/FH Spread Spectrum Technique

    Atsushi HOSHIKUKI  Michio YAMAMOTO  Satoru ISHII  Ryuji KOHNO  Hideki IMAI  

     
    PAPER

      Vol:
    E76-B No:8
      Page(s):
    984-989

    Industrial radio control systems require a high degree of safety and reliability even in operating environments where harsh interference conditions exist. In order to implement Spread Spectrum (SS) modulation techniques in industrial radio control systems, a hybrid Direct Sequence/Frequency Hopping (DS/FH) system with high speed synchronization capability was designed, implemented and evaluated. In this system, a digital matched filter was utilized for despreading the DS signal. By manipulating the despread signal and sensing the correlation peak, the frequency hopping circuit can operate without a special synchronizing circuit. The focus of this report is on an engineering sample created for the 900MHz band available as an ISM band in the U.S. In this sample, error correction code was integrated with the hybrid DS/FH which gives the system excellent narrow-band interference rejection properties and Code Division Multiple Access (CDMA) capabilities.

  • Hybrid Neural Networks as a Tool for the Compressor Diagnosis

    Manabu KOTANI  Haruya MATSUMOTO  Toshihide KANAGAWA  

     
    PAPER-Speech Processing

      Vol:
    E76-D No:8
      Page(s):
    882-889

    An attempt to apply neural networks to the acoustic diagnosis for the reciprocating compressor is described. The proposed neural network, Hybrid Neural Network (HNN), is composed of two multi-layered neural networks, an Acoustic Feature Extraction Network (AFEN) and a Fault Discrimination Network (FDN). The AFEN has multi-layers and the number of units in the middle hidden layer is smaller than the others. The input patterns of the AFEN are the logarithmic power spectra. In the AFEN, the error back propagation method is applied as the learning algorithm and the target patterns for the output layer are the same as the input patterns. After the learning, the hidden layer acquires the compressed input information. The architecture of the AFEN appropriate for the acoustic diagnosis is examined. This includes the determination of the form of the activation function in the output layer, the number of hidden layers and the numbers of units in the hidden layers. The FDN is composed of three layers and the learning algorithm is the same as the AFEN. The appropriate number of units in the hidden layer of the FDN is examined. The input patterns of the FDN are fed from the output of the hidden layer in the learned AFEN. The task of the HNN is to discriminate the types of faults in the compressor's two elements, the valve plate and the valve spring. The performance of the FDN are compared between the different inputs; the output of the hidden layer in the AFEN, the conventional cepstral coefficients and the filterbank's outputs. Furthermore, the FDN itself is compared to the conventional pattern recognition technique based on the feature vector distance, the Euclid distance measure, where the input is taken from the AFEN. The obtained results show that the discrimination accuracy with the HNN is better than that with the other combination of the discrimination method and its input. The output criteria of network for practical use is also discussed. The discrimination accuracy with this criteria is 85.4% and there is no case which mistakes the fault condition for the normal condition. These results suggest that the proposed decision network is effective for the acoustic diagnosis.

  • Interpolation of CT Slices for Laser Stereolithography

    Takanori NAGAE  Takeshi AGUI  Hiroshi NAGAHASHI  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E76-D No:8
      Page(s):
    905-911

    An algorithm interpolating parallel cross-sections between CT slices is described. Contours of equiscalar or constant-density surfaces on cross-sections are directly obtained as non-intersecting loops from grayscale slice images. This algorithm is based on a general algorithm that the authors have proposed earlier, constructing triangulated orientable closed surfaces from grayscale volumes and is particularly suited for a new technique, called laser stereolithography, which creates real 3D plastic objects using UV laser to scan and harden liquid polymer. The process of laser stereolithography is executed slice by slice, and this technique really requires some interpolation of intermediate cross-sections between slices. For visualizing, surfaces are only expected to be shaded almost continuously. The local defects are invisible and not cared about if the picture resolution is rather poor. On the contrary, topological faults are fatal to construct solid models by laser stereolithography, i.e., every contour line on cross-sections must be closed with no intersection. Not a single break of a contour line is tolerated. We already have many algorithms available for equiscalar surface construction, and it seems that if we cut the surfaces, then contour lines could be obtained. However, few of them are directly applicable to solid modeling. Marching cubes algorithm, for example, does not ensure the consistency of surface topology. Our algorithm guarantee an adequate topology of contour lines.

  • A Theory of Extended Pseudo-Biorthogonal Bases

    Hidemitsu OGAWA  Nasr-Eddine BERRACHED  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E76-D No:8
      Page(s):
    890-897

    This paper introduces the concept of an extended pseudo-biorthogonal basis" (EPBOB), which is a generalization of the concepts of an orthonormal (OB), a biorthonormal (BOB), a pseudo-orthogonal (POB), and a pseudo-biorthogonal (PBOB) bases. Let HN be a subspace of a Hilbert space H. The concept of EPBOB says that we can always construct a set of 2M (MN) elements of H but not necessarily all in HN such that like BOB any element f in HN can be expressed by fMΣm=1(f,φ*m)φm. For a better understanding and a wide application of EPBOB, this paper provides their characterization and shows how they preserve the formalism of BOB. It also shows how to construct them.

  • Magnetic Shields for HTc SQUIDs

    Kumiko IMAI  Hironori MATSUBA  Peter SPEAR  Alistair FIFE  

     
    PAPER

      Vol:
    E76-C No:8
      Page(s):
    1280-1286

    Bi2Sr2Ca1Cu2Ox thick film superconducting shields have been fabricated for use with HTc SQUIDs. Shielding factors and internal noise levels of the shields were measured using a DC SQUID magnetometer. A sample in which BSCCO was coated on the outside of a cylindrical Ag substrate exhibited larger noise levels than that with a sample in which BSCCO was coated on the inside of the Ag cylinder. The difference is explained by the thermally driven (Johnson) noise from the Ag substrate. A sample with the Ag cylinder outside the superconductor and samples with MgO substrates inside the superconductor showed good performance with a shielding factors of 10-8 and internal noise levels which did not exceed the DC SQUID magnetometer resolution (5 fTrms/Hz) at 4.2 K. In addition, the flux relaxation noise of BSCCO superconducting shields was estimated from the relaxation behavior of BSCCO.

  • Pseudonoise Sequences by Chaotic Nonlinear Maps and Their Correlation Properties

    Tohru KOHDA  Akio TSUNEDA  

     
    PAPER

      Vol:
    E76-B No:8
      Page(s):
    855-862

    A simple method is given for obtaining new families of pseudonoise (PN) sequences based on chaotic non-linear maps. Such families are worse than the Gold and the Kasami families in terms of maximum correlation values. Nevertheless, such a method has several advantages: the generation is easy, and various families with an arbitrary family size and sequence period can be obtained primarily because non-linear maps have several parameters to be secret keys for communications security. Hence these sequences are good candidates of spreading sequences for CDMA.

  • Design of Josephson Ternary Delta-Gate (δ-Gate)

    Ali Massoud HAIDAR  Fu-Qiang LI  Mititada MORISUE  

     
    PAPER-Computer Hardware and Design

      Vol:
    E76-D No:8
      Page(s):
    853-862

    A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

  • A Real-Time Scheduler Using Neural Networks for Scheduling Independent and Nonpreemptable Tasks with Deadlines and Resource Requirements

    Ruck THAWONMAS  Norio SHIRATORI  Shoichi NOGUCHI  

     
    PAPER-Bio-Cybernetics

      Vol:
    E76-D No:8
      Page(s):
    947-955

    This paper describes a neural network scheduler for scheduling independent and nonpreemptable tasks with deadlines and resource requirements in critical real-time applications, in which a schedule is to be obtained within a short time span. The proposed neural network scheduler is an integrate model of two Hopfield-Tank neural network medels. To cope with deadlines, a heuristic policy which is modified from the earliest deadling policy is embodied into the proposed model. Computer simulations show that the proposed neural network scheduler has a promising performance, with regard to the probability of generating a feasible schedule, compared with a scheduler that executes a conventional algorithm performing the earliest deadline policy.

  • Breast Tumor Classification by Neural Networks Fed with Sequential-Dependence Factors to the Input Layer

    Du-Yih TSAI  Hiroshi FUJITA  Katsuhei HORITA  Tokiko ENDO  Choichiro KIDO  Sadayuki SAKUMA  

     
    PAPER-Medical Electronics and Medical Information

      Vol:
    E76-D No:8
      Page(s):
    956-962

    We applied an artificial neural network approach identify possible tumors into benign and malignant ones in mammograms. A sequential-dependence technique, which calculates the degree of redundancy or patterning in a sequence, was employed to extract image features from mammographic images. The extracted vectors were then used as input to the network. Our preliminary results show that the neural network can correctly classify benign and malignant tumors at an average rate of 85%. This accuracy rate indicates that the neural network approach with the proposed feature-extraction technique has potential utility in the computer-aided diagnosis of breast cancer.

  • FOREWORD

    Takeshi KOBAYASHI  

     
    FOREWORD

      Vol:
    E76-C No:8
      Page(s):
    1229-1230
  • On a Recent 4-Phase Sequence Design for CDMA

    A. Roger HAMMONS, Jr.  P. Vijay KUMAR  

     
    INVITED PAPER

      Vol:
    E76-B No:8
      Page(s):
    804-813

    Recently, a family of 4-phase sequences (alphabet {1,j,-1,-j}) was discovered having the same size 2r+1 and period 2r-1 as the family of binary (i.e., {+1, -1}) Gold sequences, but whose maximum nontrivial correlation is smaller by a factor of 2. In addition, the worst-case correlation magnitude remains the same for r odd or even, unlike in the case of Gold sequences. The family is asymptotically optimal with respect to the Welch lower bound on Cmax for complex-valued sequences and the sequences within the family are easily generated using shift registers. This paper aims to provide a more accessible description of these sequences.

  • An Architecture for Parallelism of OPS5 Production Systems

    Tsuyoshi KAWAGUCHI  Etsuro HONDA  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E76-D No:8
      Page(s):
    935-946

    In this paper we propose an architecture and an algorithm for the parallel execution of OPS5 production systems. It is known that current OPS5 production system interpreters spend almost 90% of their execution time in the match step. Thus, in this paper we focus on the speedup of the match step. The match algorithm used in OPS5 is called Rete and the algorithm uses a special kind of a date-flow network compiled from the left hand sides of rules. To achieve the maximum degree of parallelism of a given OPS5 program by as few processors as possible, the proposed parallel machine uses loosely coupled multiprocessors. Parallel machines designed for fine-grain parallelism, such as DADO, also use loosely coupled multiprocessors. However, the proposed machine differs from such machines at the following points: use of powerful processors which have large amounts of memories and small cycle times; use of a shared Rete network (parallel machines designed for fine-grain parallelism use an unshared Rete network); high hardware utilization. Basic ideas of the proposed parallel machine are as follows. (1) Use of a modified Rete network in which node sharing is used only for constant-test nodes and each memory node is lumped with the child two-input node. (2) Static allocation of the nodes of the modified Rete network onto processors. (3) Partition of the set of processors into three subsets: constant-test node processors, two-input node processors and conflict-set processors. (4) Use of a ring network for the interconnection network among two-input node processors. In addition to an architecture for parallel execution of OPS5 production systems, we propose a scheme for mapping the modified Rete network into the proposed architecture. The results of simulation experiments showed that the proposed architecture is promising for parallel execution of OPS5 production systems.

  • An Architecture for High Speed Array Multiplier

    Farhad Fuad ISLAM  Keikichi TAMARU  

     
    PAPER-Computer Aided Design (CAD)

      Vol:
    E76-A No:8
      Page(s):
    1326-1333

    High speed multiplication of two n-bit numbers plays an important role in many digital signal processing applications. Traditional array and Wallace multipliers are the most widely used multipliers implemented in VLSI. The area and time (=latency) of these two multipliers depend on operand bit-size, n. For a particular bit-size, they occupy fixed positions in some graph which has area and time along the x and y-axes respectively. However, many applications require a multiplier which has an 'intermediate' area-time characteristics with the above two traditional multipliers occupying two extreme ends of above mentioned area-time curve. In this paper, we propose such an intermediate multiplier which trades off area for time. It has higher speed (i.e., less latendy) but more area than a traditional array multiplier. Whereas when compared with a traditional Wallace multiplier, it has lower speed and area. The attractive point of our multiplier is that, it resembles an array multiplier in terms of regularity in placement and inter-connection of unit computation cells. And its interesting feature is that, in contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts among its computation cells. In this paper, we investigate on the area-time complexity of our proposed multiplier and discuss on its characteristics while comparing with some contemporary multiplers in terms of latency, area and wiring complexity.

38801-38820hit(42756hit)