In our recent work, a forward test generation method for sequential circuits by using a single time frame was proposed. In order to improve the effectiveness of the method, we introduced an extended mode which can handle the two time frames for a hard-to-test fault and a state escaping phase which can detect a sequence of unsuitable states for test generation. The experimental results show that the improved method is effective in generating higher coverage tests with a small number of tests.

This paper deals with study results on the effect of nonlinear amplification in the CDMA system using offset-QPSK signals bandlimited with a square-root cosine roll-off filter. As a result of the study, it is shown that the nonlinear amplification does not affect bit error rate performance with reasonable out-of-band emission characteristics when the roll-off factor of the transmit filter is one.

A radial line slot antenna (RLSA) is a high gain and high efficiency planar array. A single-layered RLSA is much simple in structure but the slot length must be varied to synthesize uniform aperture illumination. These are now commercialized for 12GHz band DBS reception. In RLSAs, considerable power is dissipated in the termination as is common to other traveling wave antennas; the uniform aperture illumination is not the optimum condition for high gain in RLSAs. Authors proposed a theoretical method reducing the termination loss for further efficiency enhancement. This paper presents the measured performances of the SL-RLSAs of this design with non-uniform aperture illumination. The efficiency enhancement of about 10% is observed; the measured gain of 36.7dBi (87%) and 32.9dBi (81%) for a 0.6mφ and 0.4mφ antennas respectively verify this technique.

A novel external clocking magnetic disk recording channel is proposed and examined. Timing not only for data recovery but for recording is given by a bit clock which is synchronized with dedicated clock marks on patterned discrete track media. Jitter of the bit clock is 2.5 ns (rms), which is good enough for data rates up to about 20 Mbit/s. Using an MR/Inductive head and PRML (Partial Response Maximum Likelihood) signal processing, an error rate of 110-6 is obtained at linear density 3146 bit/mm.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

A new neural network system for object recognition is proposed which is invariant to translation, scaling and rotation. The system consists of two parts. The first is a preprocessor which obtains projection from the input image plane such that the projection features are translation and scale invariant, and then adopts the Rapid Transform which makes the transformed outputs rotation invariant. The second part is a neural net classifier which receives the outputs of preprocessing part as the input signals. The most attractive feature of this system is that, by using only a simple shift invariant transformation (Rapid transformation) in conjunction with the projection of the input image plane, invariancy is achieved and the system is of reasonably small size. Experiments with six geometrical objects with different degrees of scaling and rotation shows that the proposed system performs excellent when the neural net classifier is trained by the Cascade-correlation learning algorithm proposed by Fahlman and Lebiere.

In this paper we propose a method of formal verfication of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. We concretely illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method.

We propose a new architecture of Functional Memory type Parallel Processor (FMPP) architectures called bit-parallel block-parallel (BPBP) FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel processor architecture that has a memory-based simple two-dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of processors. So far, a bit-serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP. In a BSWP FMPP, each word of a CAM works as a processor, and the amount of hardware is minimized by abopting a bit-serial operation, thus maximizing integration scale. The BSWP FMPP, however, does not allow operations between two words, which restriction limits the applicability of the BSWP FMPP. On the other hand, the proposed BPBP FMPP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words called a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and is suitable for various applications.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.

This letter proposes an LSP quantizing method which uses interframe correlation of the parameters. The quantized parameters are represented as a moving average of code vectors. Using this method, LSP parameters are quantized efficiently and the degradation of decoded parameters caused by bit errors affects only a few following frames.

Scaling-down of MOSFETs (metal-oxide-semiconductor field effect transistors can be divided to semi-classical and quantum mechanical one. In the regime of semi-classical scaling-down the behavior of electrons and holes can be well described with the effective mass approximation and in the regime of quantum mechanical scaling-down the characteristics of electrons and holes as wave becomes markedly. The minimum size limit of MOSFETs scaled down in semi-classical regime is mainly determined by the subthreshold characteristics and the short channel effect on the threshold voltage and 0.1 µm will be the minimum channel length from practical viewpoints. Scaling down of MOSFETs enhances their operational speed, but the substrates with high resistivity which are often used in SOI (silicon on insulator) substrates result longer dielectric relaxation time. While the dielectric relaxation time becomes longer than the reciprocal of signal frequency, the semiconductors work as lossy dielectrics and may lead to new types of dynamic circuits. Modification of material properties utilizing the wave nature of electrons is an illustration of quantum mechanical way to improve characteristics of MOSFETs. Suppression of optical phonon scattering of two dimensional electrons by introducing two dimensional array of quantum dots into substrates is expected to improve high field characteristics of material. Brillouin zone folding is another way to control the band structure of materials, especially to make the indirect transition band structure to the direct transition band structure. Heat transfer from a chip severely limits the number of devices which can be integrated on the chip. Reduction of signal charge to electronic elementary charge, that is quantum limit, is expected to be useful for realization of nano-power electronics.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

A new transfer mode and a switching architecture which can support loss free and no delay jitter service class with shorter switching delay compared with "stop and go queueing scheme" is proposed. This scheme combines ATM scheme with hierarchical STM framing concept.

The authors examined the effect of feedbacking information on learners of their test results obtained through computerized tests. The learner's acceptability of computerized tests was revealed to be improved by distribution and explanation of newly devised feedback charts including data on one's response history and response latency during computerized testing that was carried out in formative evaluation. The feedback chart composed of graphic representation of relationship between degree of difficulty of each question and its response latency got a particularly high evaluation among learners. It was revealed that types of feedback chart that stood highest in learner's estimate varied with the learner traits. This observation will serve to develop educational systems that incorporate computerized tests into school lessons.

In this letter, we study on the sensitivity to the electrical stimulus pulse for biomedical electronics for the purpose to make a tactile vision substitution system for binds. We derive the equivalent circuit of finger by measuring sensitive voltages with various touch condition and various DC voltage. And we consider to the sensitivity of finger against electrical stimulus pulse. In order to convert the sense of sight to tactile sense, we consider four types of touch condition and various types of pulse. It is shown that the sensitivity of finger to electrical stimulus pulse is determined by duty-ratio, frequency, hight of pulse and the type of touch condition. In the case that duty-ratio is about 20%, frequency is within about 60-300Hz and touch condition is A-4 type, the sensitive voltage becomes the lowest. With this result, a tactile vision substitution system can be developed and the system will be used to transfer various infomations to blinds without paper.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing; both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.