This paper's main objective is to clearly describe the construction of a universal code for minimizing Davisson's minimax redundancy in a range where the true model and stochastic parameters are unknown. Minimax redundancy is defined as the maximum difference between the expected persymbol code length and the per-symbol source entropy in the source range. A universal coding scheme is here formulated in terms of the weight function, i.e., a method is presented for determining a weight function which minimizes the minimax redundancy even when the true model is unknown. It is subsequently shown that the minimax redundancy achieved through the presented coding method is upper-bounded by the minimax redundancy of Rissanen's semi-predictive coding method.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

In this paper, we show that without any unproven assumption, there exists a "four" move blackbox simulation perfect zero-knowledge interactive proof system of computational ability for any random self-reducible relation R whose domain is in BPP, and that without any unproven assumption, there exists a "four" move blackbox simulation perfect zero-knowledge interactive proof system of knowledge on the prime factorization. These results are optimal in the light of the round complexity, because it is shown that if a relation R has a three move blackbox simulation (perfect) zero-knowledge interactive proof system of computational ability (or of knowledge), then there exists a probabilistic polynomial time algorithm that on input x ∈ {0, 1}*, outputs y such that (x, y)∈R with overwhelming probability if x ∈dom R, and outputs "⊥" with probability 1 if x dom R.

Based on distributed artificial intelligence technology, the paper proposes a distributed expert system for distribution system planning. The developed expert system is made up of a set of problem-solving agents that autonomously process local tasks and cooperatively interoperate with each other by a shared database in order to reach a proper distribution plan. In addition, a two-level control mechanism composed of local-control and meta-control is also proposed to achieve a high degree of goodness in distribution system planning. To demonstrate its effect, the distributed expert system is implemented on basis of NASA's CLIPS and SUN's RPC and applied to the planning of distribution system in Taiwan. Test results indicate that the distributed expert system assists system planners in making an appropriate plan.

In this paper we discuss a neural network model that can recognize patterns rotated at various angles. The model employs copy learning, a learning method entirely different from those used in conventional models. Copy-Learning is an effective learning method to attain the desired objective in a short period of time by making a copy of the result of basic learning through the application of certain rules. Our model using this method is capable of recognizing patterns rotated at various angles without requiring mathematical preprocessing. It involves two processes: first, it learns only the standard patterns by using part of the network. Then, it copies the result of the learning to the unused part of the network and thereby recognizes unknown input patterns by using all parts of the network. The model has merits over the conventional models in that it substantially reduces the time required for learning and recognition and can also recognize the rotation angle of the input pattern.

This paper's main objective is to analyze several procedures which select the model g among a set G of stochastic models to minimize the value of an information criterion in the form of L(g)H[g](zn)+(k(g)/2)c(n), where zn is the n observed data emitted by an information source θ which consists of the model gθ∈G and k(gθ) mutually independent stochastic parameters in the model gθ∈G, H[g](zn) is (-1) (the maximum log likelihood value of the data zn with respect to a model g∈G), and c(n) is a predetermined function (penalty function) of n which controls the amount of penalty for increasing the model size. The result is focused on specific performances when the information criteria are applied to the framework of so-called state decomposition. Especially, upper bounds are derived of the following two performance measures for each penalty function c(n): the error probability of the model selection, and the average Kullback-Leibler information between the true information source and the estimated information source.

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

A novel external clocking magnetic disk recording channel is proposed and examined. Timing not only for data recovery but for recording is given by a bit clock which is synchronized with dedicated clock marks on patterned discrete track media. Jitter of the bit clock is 2.5 ns (rms), which is good enough for data rates up to about 20 Mbit/s. Using an MR/Inductive head and PRML (Partial Response Maximum Likelihood) signal processing, an error rate of 110-6 is obtained at linear density 3146 bit/mm.

In this paper we propose a method of formal verfication of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. We concretely illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method.

A new neural network system for object recognition is proposed which is invariant to translation, scaling and rotation. The system consists of two parts. The first is a preprocessor which obtains projection from the input image plane such that the projection features are translation and scale invariant, and then adopts the Rapid Transform which makes the transformed outputs rotation invariant. The second part is a neural net classifier which receives the outputs of preprocessing part as the input signals. The most attractive feature of this system is that, by using only a simple shift invariant transformation (Rapid transformation) in conjunction with the projection of the input image plane, invariancy is achieved and the system is of reasonably small size. Experiments with six geometrical objects with different degrees of scaling and rotation shows that the proposed system performs excellent when the neural net classifier is trained by the Cascade-correlation learning algorithm proposed by Fahlman and Lebiere.

We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.

This paper presents a new redundant fault identification algorithm, REDUCT. This algorithm handles the redundant fault identification problem by transforming a given circuit into another circuit. It also reduces the complexity of the transformed circuit, which is caused by a large number of reconvergences and head lines, using five circuit reduction techniques. Further, it proves redundancies and generates test patterns for hard faults more efficiently than conventional test pattern generation algorithms. We obtained 100% fault coverage for all ISCAS85 benchmark circuits using REDUCT following the execution of the test pattern generation algorithm N2-V.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

An estimation method of region is presented, in which a solution path of the so-called Newton type homotopy equation in guaranteed to exist, it is applied to a certain class of uniquely solvable nonlinear equations. The region can be estimated a posteriori, and its upper bound also can be estimated a priori.

Scaling-down of MOSFETs (metal-oxide-semiconductor field effect transistors can be divided to semi-classical and quantum mechanical one. In the regime of semi-classical scaling-down the behavior of electrons and holes can be well described with the effective mass approximation and in the regime of quantum mechanical scaling-down the characteristics of electrons and holes as wave becomes markedly. The minimum size limit of MOSFETs scaled down in semi-classical regime is mainly determined by the subthreshold characteristics and the short channel effect on the threshold voltage and 0.1 µm will be the minimum channel length from practical viewpoints. Scaling down of MOSFETs enhances their operational speed, but the substrates with high resistivity which are often used in SOI (silicon on insulator) substrates result longer dielectric relaxation time. While the dielectric relaxation time becomes longer than the reciprocal of signal frequency, the semiconductors work as lossy dielectrics and may lead to new types of dynamic circuits. Modification of material properties utilizing the wave nature of electrons is an illustration of quantum mechanical way to improve characteristics of MOSFETs. Suppression of optical phonon scattering of two dimensional electrons by introducing two dimensional array of quantum dots into substrates is expected to improve high field characteristics of material. Brillouin zone folding is another way to control the band structure of materials, especially to make the indirect transition band structure to the direct transition band structure. Heat transfer from a chip severely limits the number of devices which can be integrated on the chip. Reduction of signal charge to electronic elementary charge, that is quantum limit, is expected to be useful for realization of nano-power electronics.

To investigate necessary conditions for the object recognition by simulations using neural network models is one of ways to acquire suggestions for understanding the neuronal representation of objects in the brain. In the present study, we trained a three layered neural network to form a geometrical feature representation in its output layer using back-propagation algorithm. After training using 73 learning examples, 65 testing patterns made by various combinations of above features could be recognized with the network at a rate of 95.3% appropriate response. We could classify four types of hidden layer units on the basis of effects on the output layer.

Recently, there has been increasing interest in Code Division Multiplex (CDM) systems. We reported the CDM system using the -chip shift multiplex operation. So far the performance of this system evaluated under the optimum . In this letter, we evaluate an influence of the phase difference between the groups on BER performance in 2M-plex system.

A speech coding scheme at 3.6 kbit/s has been proposed. The scheme is based on CELP (Code Excited Linear Prediction) with pitch synchronous innovation, which means even random codevectors as well as adaptive codevectors have pitch periodicity. The quality is comparable to 6.7 kbit/s VSELP coder for the Japanese cellular radio standard.