Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.

This paper reviews the potential possibility and present status of trans-polyacetylene research toward realization of soliton molecular devices utilizing characteristics of the quasi-one-dimensional conductor. Properties of solitons in polyacetylene are summarized from a point of view to produce a new microelectronics beyond Si-LSI's. The limiting performance of soliton LSI's are roughly estimated. One bit information is stored in only 420 2. The information transmission rate of a wiring is 2104 Gb/s. The delay time per gate is 0.05 ps. For realization of this high performance devices, a lot of research must be carried out in future. A new circuit with new principles of operations must be developed to achieve the performance, where a localized soliton or a localized group of solitons are treated. Some systems, which may lead to development of logic circuits, are proposed. The problems in crystal quality and fabrication process are also discussed and some means against them are presented.

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

Embossed disks with discrete magnetic tracks and servo marks are proposed and evaluated. The tracks and the servo marks are made by etching the glass substrate. The guard band depth was decided to be 0.2 µm. Using the disks, the head positioning accuracy of 0.09µm (rms) and the recording density of 192 tracks per millimeter were demonstrated.

Correlation between the surface-SAR and external magnetic near-field in a realistic head model for 1.5GHz microwave far-field exposure is described. The regression relation is shown between the one gram averaged SAR and squared external magnetic field on the cross sectional perimeter of the head model.

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing; both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

A speech coding scheme at 3.6 kbit/s has been proposed. The scheme is based on CELP (Code Excited Linear Prediction) with pitch synchronous innovation, which means even random codevectors as well as adaptive codevectors have pitch periodicity. The quality is comparable to 6.7 kbit/s VSELP coder for the Japanese cellular radio standard.

A new transfer mode and a switching architecture which can support loss free and no delay jitter service class with shorter switching delay compared with "stop and go queueing scheme" is proposed. This scheme combines ATM scheme with hierarchical STM framing concept.

Reflection mode diffraction tomography is expected to reconstruct a higher resolution image than transmission mode. Its image reconstruction problem, however, in the many cases of practical uses becomes ill-posed one. In this paper, a new reconstruction method of limited angle reflection mode diffraction tomography using maximum entropy method is proposed. Results of simulation showed that the method was able to reconstruct the better quality images than IR method poposed by Kak, et al.

The already reported physical glossiness such as Mirror glossiness, indistinctness-degree glossiness, etc. are not proportional to the psycological glossiness which is the standard of the gloss, in cases of various colored specimens. Thus, in order to obtain a glossiness proportional to the psycological glossiness, first, the brightness distribution of the colored specimens was measured. Then, it was transformed to bring the form of the measured brightness distribution close to the visual distinctness-begree distribution, by the expand-reduce transformation technique. From the transformed distribution curve, the new glossiness G(H, V, C) was defined as functions of hue H, lightness V, saturation C and the indistinctness-degree glossiness GID. This new glossiness G(H, V, C) was applied to the Munsell color atlas papers and the high glossy colored papers, and then it was confirmed to be in proportion to the psychological glossiness GPh.

This letter reports a high-sensitivity GaAs decision IC for ultra-high-speed optical transmission systems. The IC was designed using LSCFL (Low-power Source Coupled FET Logic) and fabricated with 0.2-µm-gate-length MESFETs with a cut-off frequency of 50GHz. The input voltage sensitivity was 35mV at 10Gbit/s. This is the highest sensitivity ever reported for a MESFET decision IC.

We have fabricated a thin head composed of a double layer magnetoresistive (MR) reproducing element and an inductive recording element for high density rigid disk drives. We have also developed a low noise reproducing amplifier IC whose input noise level is 0.3nV/Hz. Our experimental results indicate that equal electrical potential between the exposed area of the MR element and the medium's surface improves the durability of our MR head.

Recently, there has been increasing interest in Code Division Multiplex (CDM) systems. We reported the CDM system using the -chip shift multiplex operation. So far the performance of this system evaluated under the optimum . In this letter, we evaluate an influence of the phase difference between the groups on BER performance in 2M-plex system.

A new type jacket cutter for optical fibers is designed, and it is confirmed experimentally that its performance is superior to those of the conventional cutters. Using this new cutter which is mainly consisted of a rotatable fiber holder and a pair of blades separated by a distance of 0.3-0.4mm, only the tight jacket is cut and removed while the primary coating and the fiber are kept intact. As the result, the probability of damage to the fiber surface during jacket removal is reduced to about 0% compared to 10% found in the case of a conventional cutter. This result is useful to increase the reliability of optical fibers during assembling efforts.

In order to describe the flow passing through the glottis, we constructed a dynamic three-dimensional finite element model of the human larynx. The transient flow fields in the laryngeal model were calculated to examine the dynamic effects generated by the vocal fold vibration. A phase difference between the upper and lower edges of the vocal folds was included in the model to investigate the effect of the glottal shapes on pressure-flow relationships in the larynx during the vocal fold vibration. Using STAR-CD thermofluids analysis system, which is capable of treating the transient flow in moving-boundary situations with finite volume method, we solved the viscous incompressible Navier-Stokes equations to investigate the glottal flows and transglottal pressures as a function of the vocal fold vibration. The results were compared to the uniform glottis model and the theoretical model proposed by Ishizaka and Matsudaira, respectively. The effects of dynamic factors on the pressure distributions and flow patterns in the larynx resulting from the vocal-fold vibration were also discussed.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

Japan's PARTNERS Project, one of the programmes of ISY advocated by UN, has just started. This letter is a brief introduction of the trials being carried out by the partners in the University of Electro-communications under the Project. The focus is on the distance education and training via ETS-V overcoming the geographical extent and the cultural diversity of the Asia-Pacific Region.

In this letter, the effectiveness of the quasi-TEM approximation is studied for the microstrip line including optically induced semiconductor plasma region. This approximation is considered to be efficient under several restrictions such as the upper limit of the microwave frequency and the plasma density.

In this paper, we present an efficient method for the fault simulation of the reconvergent fan-out stem. Our method minimizes the fault propagating region by analyzing the topology of the circuit, whose region is smaller than that of Tulip's. The efficiency of our method is illustrated by experimental results for a set of benchmark circuits.

We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.