Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.

Behavior of solutions related to an accuracy exp(-1/ε) is studied. Computer results are given, and examined from the view-point of non-standard analysis. The experimental results raise some important questions on the computer study of slow-fast systems.

The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

The most commonly used activation function in Backpropagation learning is sigmoidal while linear function is also sometimes used at the output layer with the view that choice between these activation functions does not make considerable differences in network's performance. In this letter, we show distinct performance between a network with linear output units and a similar network with sigmoid output units in terms of convergence behavior and generalization ability. We experimented with two types of cost functions, namely, sum-squared error used in standard Backpropagation and log-likelihood recently reported. We find that, with sum-squared error cost function and hidden units with nonsteep sigmoid function, use of linear units at the output layer instead of sigmoidal ones accelerates the convergence speed considerably while generalization ability is slightly degraded. Network with sigmoid output units trained by log-likelihood cost function yields even faster convergence and better generalization but does not converge at all with linear output units. It is also shown that a network with linear output units needs more hidden units for convergence.

A systematic method is proposed to generate a random image with a known correlation function and the modified Laplace distribution; the modified Laplace distribution includes the one-side exponential distribution and the Laplace distribution as a special case. Several random images with an isotropic correlation and the modified Laplace distribution are generated and displayed in figures.

This paper presents efficient algorithms for finding the largest tree S such that there are vertex disjoint subtrees S1, , S (k1) of T each of which is isomorphic to S and every leaf of T is a leaf of some Si. The algorithms are useful for learning a macro table.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

High-speed learning of neural networks using the multifrequency oscillation method is demonstrated for first time. During the learning of an analog neural network integrated circuit implementing the exclusive-OR' logic, weight and threshold values converge to steady states within 2 ms for a learning speed of 2 mega-patterns per second.

This paper presents ceramic multi-layer substrates for mobile communication using alumina-glass composite ceramics and co-fired copper conductors. Electrical characteristics in GHz frequencies of the substrate, copper conductor, transmission line, via hole and coupling between the striplines were evaluated. The results showed that the ceramic multi-layer substrate had good electrical characteristics enough for GHz-band applications. Using the ceramic multi-layer substrates, one can drastically reduce the size of RF circuit boards for mobile communication equipment.

Algorithms for computing channel capacity have been proposed by many researchers. Recently, one of the authors proposed an efficient algorithm using Newton's method. Since this algorithm has local quadratic convergence, it is advantageous when we want to obtain a numerical solution with high accuracy. In this letter, it is shown that this algorithm can be extended to the algorithm for computing the constrained capacity, i.e., the capacity of discrete memoryless channels with linear constraints. The global convergence of the extended algorithm is proved, and its effectiveness is verified by numerical examples.

As is well known, Linard's equation +µf (χ)+g(χ)=0 represents a wide class of oscillatory circuits as an extension of van der Pol's equation, and Linard's theorem guarantees the existence of a unique periodic solution which is orbitally stable. However, we sometimes meet such cases in engineering applications that the symmetry of the equation is violated, for instance, by a constant bias force. While, it has been known that asymmetric Linard's equation can have more than one periodic solution. The problem of finding the maximum number of such solutions, known as a special case of Hilbert's sixteenth problem, has recently been solved by T. Koga, one of the present authors. This paper first describes fundamental theorems due to T. Koga, and presents a solution to the synthesis problem of asymmetric Linard's systems, which generates an arbitrarily prescribed number of limit cycles, and which is considered to be important in relation to the stability of Linard's systems. Then, as application of this result, we give a method of determining parameters included in Linard's systems which may produce two limit cycles depending on the parameters. We also give a Linard's system which have three limit cycles. In addition, a new result on the parameter dependency of the number of limit cycles is presented.

Behavior modeling of objects is critical in object-oriented design. In particular, it is essential to preserve integrity constraints on object behavior in application environments where objects of various classes dynamically interact with each other. In order to provide a stable design technique, a behavior model using the notion of the life cycle schema of a class is proposed. To model the aspect of behavioral abstraction of objects, the notion of schema refinement together with a diagrammatic representation technique is also defined. In this framework, a formalization of behavior constraints on objects which interact with each other is proposed together with its graphical representation. Verification rules of consistency of behavior constraints are also discussed. In order to perform certain functions, several partner objects of the same or different classes should collaborate establishing client-server relationships. The contract of a class is defined as a collection of responsibilities of a server class to a client class where each responsibility is specified in the form of the script. To achieve a high degree of systems integrity, a procedure to derive scripts from behavior constraints on collaborating partners is developed. It is also critical to evenly distribute responsibilities to partner objects. A delegation is placing a whole or a part of responsibilities of an object in charge of other objects. Based on the design principle delegation along the aggregation hierarchy,' a unified design approach to delegation that enables to reorganize scripts in constraints preserving way is proposed.

This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.

In a cellular system for mobile communications, every service area is divided into a number of cells for utilizing the frequency spectrum efficiently. Service areas for such systems are two dimensional, however, the analysis of the characteristics of the communication traffic for the areas are quite complicated, since the motion of the vehicles in the area can not be predicted precisely. For making the analysis easily, the areas are assumed to be band-shaped like a highway. Furthermore, in the analysis, the traffic offered to a cell is assumed to be stationary. In actual systems, the density of vehicles and the offered communication traffic is not stationary, so that many differences exist between the analysis and the actual systems. This paper presents an analysis method using state equations. The equations represent the transient characteristics of mobile communication traffic when a band-shaped service area is assumed. The transition is made by accidents or congestion, and causes the rapid offered traffic change in a communication system. In the method, numerical analysis is made under the consideration of "handoff" operation. The operation consists of surrendering the channel used in the previous cell and reassigning a new channel when the vehicle crosses the cell boundary. The analytical results are compared with the simulations, and the two results show good agreement. The method presented in this paper can be used for designing the switching system when the offered traffic changes rapidly due to accidents or congestion.

In this paper we present an Overlapped Block Gauss-Seidel (OBGS) algorithm for the solution of large scale LSEs (Linear System of Equations) based on array architecture which we have already proposed. Better partitioning for processor array usually requires (1) balanced block size, and (2) minimum coupling between blocks for better convergence. These conditions can well be satisfied by overlapping some variables in computation algorithm. The mathematical implication of overlapped partitioning is discussed at first, and some examples show the effectiveness of OBGS algorithm. Conclusion points out that the convergence properties can well be improved by proper choice of overlapped variables. An efficient algorithm is given for choosing block and variables in order to realize above conditions.

In using a natural language database interface (NLI) to access the contents of a databese, the user queries may contain terms that do not appear at all in both the NLI lexicon and the database. A friendly NLI should not reject user queries with unknown terms, but should be able to handle them, and should be able to learn new lexical items. Such capability increases the usefulness of the NLI, and allows the NLI to more cover the domain of the underlying database. Therefore, a technique to handle unknown terms is decisive in designing a friendly NLI. In this work, we discuss a method that would allow a NLI to identify the meanings of unknown database field values, and terms that are exceeding the conceptual coverage of the database, in the user queries, by engaging the user in clarification dialogues based on a database-domain hierarchy. It will be shown that the method enables the NLI lexicon to learn new lexical items at run time while the clarification dialogues, and it may provide the necessary information for generating informative answers to some particular failing user queries. Moreover, the method is an efficient means to handle queries with insufficience contextual cues. The examples throughout this work are drawn from FIFA 90, an experimental NLI to a soccer database.

A genetic method to generate a neural network which has both structure and connection weights adequate for a given task is proposed. A neural network having arbitrary connections is regarded as a virtual living thing which has genes representing its connections among neural units. Effectiveness of the network is estimated from its time sequential input and output signals. Excellent individuals, namely appropriate neural networks, are generated through generation iterations. The basic principle of the method and its applications are described. As an example of evolution from randomly generated networks to feedforward networks, an XOR problem is dealt with, and an action control problem is used for making networks containing feedback and mutual connections. The proposed method is available for designing a neural network whose adequate structure is unknown.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.