Formation process of the anodic oxide film of hafnium for use as a thin-film capacitor has been examined by the current-voltage characteristics of the anodization and the in-depth analysis of formed oxide using Auger electron spectroscopy. It is found that the oxide growth obeys three different rate laws such as the linear rate law at first and next the parabolic rate law during the constant current anodization, and then the reciprocal logarithmic rate law during the constant voltage anodization following after the constant current process. From the Auger electron spectroscopy analysis, it is found that the shape of the compositional depth profile of the grown oxide film varies associating with the rate law of oxidation obeyed. The variation of depth profile correlating with the rate law is discussed with respect to each elementary process such as the transport and/or the reaction of chemical species interpreted from the over-all behavior of anodization process. It is revealed that the stoichiometric film having an interface with sharp transition, which is favorable for obtaining excellent electrical properties of the capacitor, can be obtained under the condition that the phase-boundary reaction is the rate-determining step of the anodization. The constant voltage anodization process also satisfies such circumstances and therefore can be the favorable method for preparing highquality thin-film capacitors.

New AC-DC converters using switched-capacitor (SC) transformers are presented. The features of these circuits are as follows. (1) It does not contain any magnetic material. (2) The inrush current of the proposed converter is very small as compared with that of a condenser-input-type rectifier circuit. (3) It is realizable in a hybrid IC form. (4) It excels in size and weight when compared with reactor-type switching regulators of the same output power. As an example, an AC-DC converter using step-up SC transformers was built and tested to confirm the characteristics. The measured characteristics showed good agreement with the calculated ones.

The routings in an analog PCB (printed circuit board) mainly consist of non-rectilinear and curved lines, which significantly affect the characteristics of an electric circuit. So, a building automatic design system for an analog PCB is still regarded as a difficult problem. In this paper, a new method for modelization of PCBs is proposed, replacing the wiring and the boundary on a PCB with surface charges, and a new routing searching method satisfying the condition of minimization of the total potential energy in all regions of a PCB. Also the applicability to an analog PCB wiring design is shown. From the basic study using computer simulation, it is found that a routing searched by this method is quite similar to the Steiner tree. In the end, it is shown that this routing can be searched by the steepest descent technique.

This paper discuses the simulation of logic circuits with feedback loops for a set of input strings. Logic circuits are modeled as Mealy machines which convert an input string set to an output string set. By the simulation, we obtain a set of output strings which shows the input-output relation of the simulated circuit. The behavior of feedback loops of a logic circuit is shown to be the least-fixed-point on a lattice of string sets. The characteristics of a lattice we have used is also shown in the paper.

A new switched-capacitor (SC) pipelined analog-to-digital (A/D) converter is proposed which appears to have some speed, accuracy, and area advantages over earlier schemes. Its analog components consist of only sample-and-hold circuits and comparators. It also has a differential-type configuration and requires only a two-phase clock. An analysis based on a few assumption about characteristics of op-amps shows that the proposed circuit can achieve 13-bit conversion accuracy at a sampling rate of 8.5 Msamples/s. When an 8-bit pipelined A/D converter built with discrete components was operated statically at clock frequency 100 kHz, the maximum total conversion error including a quantizing error was about 0.7 LSB.

A neural network model for solving channel routing problem is proposed and described. Channel routing problem is one of the most important and popular phases of computer aided design of VLSI chips. Since the problem is NP-complete, many heuristic algorithms with various routing conditions have been proposed for the last decade. Recently, J.J. Hopfield has demonstrated that a neural network can provide a heuristic technique for solving optimization problem. This paper describes how channel routing problem can be solved by a neural network model proposed by Hopfield. A brief summary of Hopfield neural network model, how to construct a neural network for solving channel routing problem, and results of digital computer simulation are described. Our results show that the neural network could provide good solutions of channel routing problem. For example, it computes a solution of the number of horizontal tracks 31 for the difficult example" and by using simple compaction algorithm the solution can be improved to 28, which is optimal within our channel routing strategy.

It is generally thought to be difficult to construct the optimum control law for the non-linear systems. The number of research papers in this field is rather small, compared with those of the neighboring fields. Among them, Garrad's study of ε-perturbation to approximate the law, Nishikawa's study about quasi-optimal control and Ohkubo's proposal to approximate system's non-linearity by the tensor products should be put more importance. Yet it is still unknown whether the optimum feedback control law for any non-linear system exists or not. In this paper, the existence conditions of this control law for weak non-linear system, which is composed of linear quadratic part and weak non-linear one, are studied using the fixed point theorem. The non-linear part is contained in εg, where ε is a small positive real number and g implies non-linear function. The existence conditions of control law for this composite system is examined, assuming the initial condition to be restrained in some bounded domain. Thus, the existence conditions for the optimum control law are resulted in terms of those for certain kind of implicit function: this implicit function relates Lagrange multipliers to the state variables of the system, using the variation principle.

Computational complexity aspect of the legal firing sequence problem (LFS) and some related problems of a Petri net PN is discussed. LFS is defined by Given a Petri net PN, a firing vector X and an initial marking M, determine whether or not there is a firing sequence δ which is legal on M with respect to X?" The related problems to be discussed in this paper are (a) the generalized submarking reachability problem (GSMR), (b) the submarking reachability problem (SMR) (c) the marking reachability problem (MR) (d) the generalized submarking reachability problem on a minimum initial submarking (MIS), (e) the lower and upper bounded submarking problem (LUS), (f) the optimum firing sequence problem (OFS) and (g) the minimum initial marking problem (MIM). Their NP-completeness and polynomial-time solvability are presented. They have applications to practical problems. For example, proofs of Horn-clause propositional logic and sequence control in factory automation are formulated as MIS and OFS, respectively.

The single layer absorber has the simplest structure among electromagnetic wave absorbers. To have thin and light materials with wide frequency characteristics for this structure, carbon and ferrite are mixed with rubber in different weight ratios. This new material has both dielectric and magnetic losses, which in a single layer structure, has good absorber characteristics . In the C-band, the relative bandwidth is up to 4.6 times wider, and the absorber is thinner, compared with nonmagnetic lossy dielectric material (i.e., 1.0, 0).

The paper discusses computational complexity and approximation algorithms for the minimum initial marking problem MIM of a Petri net PN: Given PN and firing vector X, find a minimum initial marking M such that there is a firing sequence δ which is legal on M with respect to X". It is shown that MIM is NP-complete even if PN is a weakly connected marked graph with the unity edge weight and each transition having the in-degree and outdegree, at least 1 but at most 3. An O(|T|) algorithm for finding aminimum initial marking M, a solution to MIM for a state machine with the unity edge weight, and an O(|X|2) algorithm for finding a firing sequence that is legal on M with respect to X are given, where |T|, |P|and |X| denote the number of transitions, that of places, and the total sum of components of X, respectively. Some approximation algorithms for MIM are proposed, and their experimental results are presented.

In this paper we describe a new non-deterministic optimization method for standard-cell placement based on a method of theoretical physics, which we call the Trembling Spot-Check (TSC). First we discuss the analogy between a primitive cell placement system and a magnetic spin system by mapping from the placement evaluation function to the energy function, where the primitive placement system consists of the same area size cell and interconnections related to its four neighbor cells. Then we introduce a computational state calculation method using the theory for the magnetic spin system, called the `mean-field method'. The placement improvement process by TSC is similar to the energy minimization process by the mean-field method at temperature 0. To prevent the final state of the system from falling into a local minima, we adopt the redundance factor to this method by paying attention to the concept of fluctuation in statistical physics. This method of optimization, called TSC, has two such special features that it needs no annealing process and requires only one parameter definition concerning the redundancy. These two faculities in TSC make it possible to achieve the minimal solution without the bore process such as in the method of Simulated Annealing (SA). This new non-deterministic method of optimization is applied to both primitive and standard-cell placement problems. In the standard-cell placement problem each cell has the same height and various widths, and the interconnections between cells are very complicated. In the primitive placement experiments, TSC is compared with SA by the total interconnection length costs of the final states and CPU time to obtain them. In the standard-cell placement problem, the area size is evaluated. We suggest a simple model for standard-cell evaluation function derived from the area size estimation. It consists of averaged values of channel heights and their standard deviations. The results in the primitive placements show that TSC requires almost 1/10 times less CPU time than SA to achieve the same level solution. Almost the same results can be observed in the experiments of standard-cell placement.

A homotopy method is proposed for numerically solving an infinite dimensional convex optimization problem (COP). In this method, in the first place, by introducing an auxiliary COP, which is easy to solve, the original COP is imbedded into a parametric COP. Then, the Kuhn-Tucker (K-T) equation is derived which is equivalent to the parametric COP. It is shown that this K-T equation belongs to a class of Approximation proper homotopy equations. Using this, a sequence of finite dimensional approximate equations are derived for the K-T equation. It is shown that under certain mild conditions these approximate equations can be always solved by finite dimensional homotopy method and numerical solutions for them can be identified. Moreover, using the Approximation properness of the K-T equation, it is shown that from such a sequence a subsequence can always be derived which is convergent to a solution of the K-T equation. In this paper, two types of auxiliary COP's are introduced and two types of K-T equations are considered, a fixed point homotopy type and a Newton homotopy type. Since applicability is slightly different, comparison of applicability is also discussed between them.

To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.

It is well known that the RC active filter simulating the conventional LC ladder filter has a lower sensitivity than the cascade RC active filter. A number of synthesis methods for this kind of filters have recently been proposed. A new class of simulation-type RC active filter with a reduced number of operational amplifiers is proposed in this paper. First, as a prototype filter to be simulated, an LCR filter is proposed, which is obtained by connecting resistors in series with capacitors in the conventional LC filter. As this type of filter has zeros on the negative real axis of s-plane, the conventional transfer function can not be used. Then, the transfer function for this type of filter is derived. The synthesis method of an LCR ladder filter with lossy capacitors is described. The relations between the voltages and currents of the above-mentioned LCR filter are derived, and circuits for realizing these relations and method for synthesizing an odd-order filter are shown. Finally, fifth-order low-pass filter is designed and it is shown that the measured response is in a good agreement with the theoretical value. Futhermore, the element sensitivity is estimated by a computer and it is shown that the sensitivity of the proposed filter is slightly higher than that of the conventional leapfrog filter. The number of required operational amplifiers becomes lower than half that of the conventional leapfrog realization.

Given a switch-box, let C be a connection requirement. If there is a polynomial time algorithm (router) to complete C, C is said to be tractable by the algorithm. There have been proposed a number of switch-box routers but none that makes clear its tractable problems. We propose a switch-box router, or rather a principle, BOX-PEELER with a simple characterization of a class of tractable problems. BOX-PEELER is developed to be an underlying concept in switch-box routing as LEFT-EDGE method has been in 2-side channel routing.

This paper proposes a hierarchical MS synchronization network in which the slaves increased averaging numbers of phase errors along the hierarchy in order to improve the network characteristics in both jitter suppression and phase tracking. The properties of the proposed network are investigated and compared with the conventional one which uses an identical averaging number in all hierarchical slaves. The results show the proposed network has an advantage over the conventional one. With the same tracking property, the jitter accumulation in the network proposed with 9 hierarchies is suppressed about 0.8-2 dB more than that in the conventional identical one, and much higher improvements are guaranteed in a larger hierarchical MS network. The idea of using increased averaging numbers along the hierarchy can be applied to the general MS synchronization network which consists of a chain of PLLs, for instance, one can design the transfer function of the PLLs with the reduced bandwidth along the chain, to obtain a better performance in the network entirety than the conventional identical one.

This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.

Although circuit simulators based on the direct method can be applied to a wide variety of circuits, they are very time consuming. In order to speed up these simulators, the following five techniques are shown to be useful: (1) use of vector processors, (2) modification of the initial value estimation method for Newton's method, (3) improved MOS capacitance model, (4) latency exploitation method and (5) circuit decomposition method. To exploit latency, a new nonlinear equation bypass method (event driven latency checking method) that traces the circuit's active parts intensively and updates only relevant circuit equations will be proposed. It will also be shown that the circuit decomposition method is effective when combined with the latency exploitation method or when the vector processing capability of vector processors can be utilized.

Simulation circuits of grounded higher-order immittance element and immittance function using a single current conveyor are proposed. Simple filter structures with 2nd- and 3rd-order transfer function are realized by using the simulated immittance function. Circuit analysis for finding the desired simulator is carried out on computer using symbolic mathematics system.