Biomimetics is a new research field that creates innovation through the collaboration of different existing research fields. However, the collaboration, i.e., the exchange of deep knowledge between different research fields, is difficult for several reasons such as differences in technical terms used in different fields. In order to overcome this problem, we have developed a new retrieval platform, “Biomimetics image retrieval platform,” using a visualization-based image retrieval technique. A biological database contains a large volume of image data, and by taking advantage of these image data, we are able to overcome limitations of text-only information retrieval. By realizing such a retrieval platform that does not depend on technical terms, individual biological databases of various species can be integrated. This will allow not only the use of data for the study of various species by researchers in different biological fields but also access for a wide range of researchers in fields ranging from materials science, mechanical engineering and manufacturing. Therefore, our platform provides a new path bridging different fields and will contribute to the development of biomimetics since it can overcome the limitation of the traditional retrieval platform.

Hybrid analog/digital precoding has attracted growing attention for millimeter wave (mmWave) communications, since it can support multi-stream data transmission with limited hardware cost. A main challenge in implementing hybrid precoding is that the channels will exhibit frequency-selective fading due to the large bandwidth. To this end, we propose a practical hybrid precoding scheme with finite-resolution phase shifters by leveraging the correlation among the subchannels. Furthermore, we utilize the sparse feature of the mmWave channels to design a low-complexity algorithm to realize the proposed hybrid precoding, which can avoid the complication of the high-dimensionality eigenvalue decomposition. Simulation results show that the proposed hybrid precoding can approach the performance of unconstrained fully-digital precoding but with low hardware cost and computational complexity.

This paper proposes a fountain coding system which has lower decoding erasure rate and lower space complexity of the decoding algorithm than the Raptor coding systems. A main idea of the proposed fountain code is employing shift and exclusive OR to generate the output packets. This technique is known as the zigzag decodable code, which is efficiently decoded by the zigzag decoder. In other words, we propose a fountain code based on the zigzag decodable code in this paper. Moreover, we analyze the overhead, decoding erasure rate, decoding complexity, and asymptotic overhead of the proposed fountain code. As a result, we show that the proposed fountain code outperforms the Raptor codes in terms of the overhead and decoding erasure rate. Simulation results show that the proposed fountain coding system outperforms Raptor coding system in terms of the overhead and the space complexity of decoding.

The present paper proposes a dynamic spectrum access policy for multi-hop cognitive radio networks (CRNs), where the transmission in each hop suffers a delay waiting for the communication channel to become available. Recognizing the energy constraints, we assume that each secondary user (SU) in the network is powered by a battery with finite initial energy. We develop an energy-efficient policy for CRNs using the Markov decision process, which searches for spectrum opportunities without a common communication channel and assigns each sensor's decision to every time slot. We first consider a single-sensor scenario. Due to the intermittent activation of the sensor, achieving the optimal sensing schedule requires excessive complexity and is computationally intractable, owing to the fact that the state space of the Markov decision process evolves exponentially with time variance. In order to overcome this difficulty, we propose a state-reduced suboptimal policy by relaxing the constrained state space, i.e., assuming that the electrical energy of a node is infinite, because this state-reduced suboptimal approach can substantially reduce the complexity of decision-making for CRNs. We then analyze the performance of the proposed policy and compare it with the optimal solution. Furthermore, we verify the performance of this spectrum access policy under real conditions in which the electrical energy of a node is finite. The proposed spectrum access policy uses the dynamic information of each channel. We prove that this schedule is a good approximation for the true optimal schedule, which is impractical to obtain. According to our theoretical analysis, the proposed policy has less complexity but comparable performance. It is proved that when the operating time of the CRN is sufficiently long, the data reception rate on the sink node side will converge to the optimal rate with probability 1. Based on the results for the single-sensor scenario, the proposed schedule is extended to a multi-hop CRN. The proposed schedule can achieve synchronization between transmitter and receiver without relying on a common control channel, and also has near-optimal performance. The performance of the proposed spectrum access policy is confirmed through simulation.

With the availability of virtualization extension in mobile processors, e.g. ARM Cortex A-15, multiple virtual execution domains are efficiently supported in a mobile platform. Each execution domain requires high-performance graphics services for full-featured user interfaces such as smooth scrolling, background image blurring, and 3D images. However, graphics service is hard to be virtualized because multiple service components (e.g. ION and Fence) are involved. Moreover, the complexity of Graphical Processing Unit (GPU) device driver also makes harder virtualizing graphics service. In this paper, we propose a technique to virtualize the graphics architecture of Android mobile platform in KVM/ARM environment. The Android graphics architecture relies on underlying Linux kernel services such as the frame buffer memory allocator ION, the buffer synchronization service Fence, GPU device driver, and the display synchronization service VSync. These kernel services are provided as device files in Linux kernel. Our approach is to para-virtualize these device files based on a split device driver model. A major challenge is to translate guest-view of information into host-view of information, e.g. memory address translation, file descriptor management, and GPU Memory Management Unit (MMU) manipulation. The experimental results show that the proposed graphics virtualization technique achieved almost 84%-100% performance of native applications.

Feature extractor is an important component of a tracker and the convolutional neural networks (CNNs) have demonstrated excellent performance in visual tracking. However, the CNN features cannot perform well under conditions of low illumination. To address this issue, we propose a novel deep correlation tracker with backtracking, which consists of target translation, backtracking and scale estimation. We employ four correlation filters, one with a histogram of oriented gradient (HOG) descriptor and the other three with the CNN features to estimate the translation. In particular, we propose a backtracking algorithm to reconfirm the translation location. Comprehensive experiments are performed on a large-scale challenging benchmark dataset. And the results show that the proposed algorithm outperforms state-of-the-art methods in accuracy and robustness.

This paper presents an automatic hierarchical formal verification method for arithmetic circuits over Galois fields (GFs) which are dedicated digital circuits for GF arithmetic operations used in cryptographic processors. The proposed verification method is based on a combination of a word-level computer algebra procedure with a bit-level PPRM (Positive Polarity Reed-Muller) expansion procedure. While the application of the proposed verification method is not limited to cryptographic processors, these processors are our important targets because complicated implementation techniques, such as field conversions, are frequently used for side-channel resistant, compact and low power design. In the proposed method, the correctness of entire datapath is verified over GF(2m) level, or word-level. A datapath implementation is represented hierarchically as a set of components' functional descriptions over GF(2m) and their wiring connections. We verify that the implementation satisfies a given total-functional specification over GF(2m), by using an automatic algebraic method based on the Gröbner basis and a polynomial reduction. Then, in order to verify whether each component circuit is correctly implemented by combination of GF(2) operations, i.e. logic gates in bit-level, we use our fast PPRM expansion procedure which is customized for handling large-scale Boolean expressions with many variables. We have applied the proposed method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes, while any single conventional verification methods fail within a day or even more.

Quaternionic neural networks are extensions of neural networks using quaternion algebra. 3-D and 4-D quaternionic MLPs have been studied. 3-D quaternionic neural networks are useful for handling 3-D objects, such as Euclidean transformation. As for Hopfield neural networks, only 4-D quaternionic Hopfield neural networks (QHNNs) have been studied. In this work, we propose the 3-D QHNNs. Moreover, we define the energy, and prove that it converges.

In this letter, we focus on a system where N sources send n ≤ N different packets to one destination, through M ≥ N relays. Each relay employs random linear network coding to encode the packets it received by randomly choosing coefficients in a finite field Fq, then forwards it to the destination. Owing to the inherent errorprone nature of erasure channels, data packets received by the relay and the destination nodes may not be correct. We analyze the optimal throughput with respect to n, given a series of parameters and derive the upper and lower bounds of throughput performance. We also analyze the impact of the number of relays and the erasure probability on the throughput performance. Simulation results are well matched with the theoretical analysis.

This paper presents study results regarding the analytical method for performance characteristics and application scheme, which cover a feature detection scheme using a Cyclic Prefix (CP) that is attached to an OFDM signal. The detection scheme is especially important when used as a sensing technology in advanced systems such as Device-to-Device (D-to-D) or Internet of Things (IoT). Herein, we present several basic performance characteristics of the signal processing involved in feature detection, namely, the Output S/N (Signal-to-Noise power ratio) and probability density functions of the OFDM signal and the noise measured at the output of the feature detector. The Output S/Nis described by an analytical expression and is also examined by conducting a software simulation. An analytical approach is investigated by modeling the spectral density of the OFDM signal and input noise and by executing the mathematical operations such as convolutional integration on the combination of OFDM signal and noise. The analytical results coincide closely with the simulation results. As for the applications to mobile communication system, some methods of the feature detection schemes are addressed. These are an estimation method for the Input C/N (Carrier-to-Noise power ratio) and a system discrimination scheme, especially under the assumption that two OFDM systems using different CP lengths are simultaneously operated in the same frequency. Furthermore, under the condition that two OFDM signals are transmitted in an asynchronous manner, a scheme to estimate their timing offset and signal power ratio is also described.

The application of complex network theory to power grid analysis has been a hot topic in recent years, which mainly manifests itself in four aspects. The first aspect is to model power system networks. The second aspect is to reveal the topology of the grid itself. The third aspect is to reveal the inherent vulnerability and weakness of the power network itself and put forward the pertinent improvement measures to provide guidance for the construction of power grid. The last aspect is to analyze the mechanism of cascading failure and establish the cascading fault model of large power failure. In the past ten years, by using the complex network theory, many researchers have investigated the structural vulnerability of power grids from the point of view of topology. This letter studies the structural vulnerability of power grids according to the effect of selective node removal. We apply several kinds of node centralities including recently-presented second-order centrality (SOC) to guide the node removal attack. We test the effectiveness of all these centralities in guiding the node removal based on several IEEE power grids. Simulation results show that, compared with other node centralities, the SOC is relatively effective in guiding the node removal and can destroy the power grid with negative degree-degree correlation in less steps.

To use millimeter wave bands in future cellular and outdoor wireless networks, understanding the multipath cluster characteristics such as delay and angular spread for different polarization is very important besides knowing the path loss and other large scale propagation parameters. This paper presents result from analysis of wide-band full polarimetric double directional channel measurement at the millimeter wave band in a typical urban pico-cell environment. Only limited number of multipath clusters with gains ranging from -8dB to -26.8dB below the free space path loss and mainly due to single reflection, double reflection and diffraction, under both line of sight (LOS) and obstructed LOS conditions are seen. The cluster gain and scattering intensity showed strong dependence on polarization. The scattering intensities for ϑ-ϑ polarization were seen to be stronger compared to ϕ-ϕ polarization and on average 6.1dB, 5.6dB and 4.5dB higher for clusters due to single reflection, double reflection and scattering respectively. In each cluster, the paths are highly concentrated in the delay domain with delay spread comparable to the delay resolution of 2.5ns irrespective of polarization. Unlike the scattering intensity, the angular spread of paths in each cluster did not show dependence on polarization. On the base station side, average angular spread in azimuth and in elevation were almost similar with ≤3.3° spread in azimuth and ≤3.2° spread in elevation for ϑ-ϑ polarization. These spreads were slightly smaller than those observed for ϕ-ϕ polarization. On the mobile station side the angular spread in azimuth was much higher compared to the base station side. On average, azimuth angular spread of ≤11.4° and elevation angular spread of ≤5° are observed for ϑ-ϑ polarization. These spreads were slightly larger than in ϕ-ϕ polarization. Knowing these characteristics will be vital for more accurate modeling of the channel, and in system and antenna design.

In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.

This study proposes an effective pseudo relevance feedback method for information retrieval in the context of question answering. The method separates two retrieval models to improve the precision of initial search and the recall of feedback search. The topic-preserving query expansion links the two models to prevent the topic shift.

Previously, it is not obvious to what extent was accepted for the assessors when we see the 3D image (including multi-view 3D) which the luminance change may affect the stereoscopic effect and assessment generally. We think that we can conduct a general evaluation, along with a subjective evaluation, of the luminance component using both the S-CIELAB color space and CIEDE2000. In this study, first, we performed three types of subjective evaluation experiments for contrast enhancement in an image by using the eight viewpoints parallax barrier method. Next, we analyzed the results statistically by using a support vector machine (SVM). Further, we objectively evaluated the luminance value measurement by using CIEDE2000 in the S-CIELAB color space. Then, we checked whether the objective evaluation value was related to the subjective evaluation value. From results, we were able to see the characteristic relationship between subjective assessment and objective assessment.

Silicon-on-insulator (SOI) has become one of the most famous materials in recent years, especially in silicon photonics applications. This paper presents a comparative performance of a SOI-based optical interconnect (OI) vs. an electrical interconnect (EI) for high-speed performances at a circuit level. The SOI-based optical waveguide was designed using OptiBPM to obtain a single mode condition (SMC). Then, the optical interconnect (OI) link was simulated in OptiSPICE and was tested as an interconnection in two-stage CS amplifiers. The results showed that the two-stage CS amplifier using OI offered several advantages in terms of electrical performances, such as voltage gain, frequency bandwidth, slew rate, and propagation delay, which makes it superior to the EI.

With rapid increase of the number of applications as well as the sizes of data, multi-query processing on the MapReduce framework has gained much attention. Meanwhile, there have been much interest in skyline query processing due to its power of multi-criteria decision making and analysis. Recently, there have been attempts to optimize multi-query processing in MapReduce. However, they are not appropriate to process multiple skyline queries efficiently and they also require modifications of the Hadoop internals. In this paper, we propose an efficient method for processing multi-skyline queries with MapReduce without any modification of the Hadoop internals. Through various experiments, we show that our approach outperforms previous studies by orders of magnitude.

The growth in the amount of information available on the Internet and thousands of user queries per second brings huge challenges to the index update and query processing of search engines. Index compression is partially responsible for the current performance achievements of existing search engines. The selection of the index compression algorithms must weigh three factors, i.e., compression ratio, compression speed and decompression speed. In this paper, we study the well-known Simple-9 compression, in which exist many branch operations, table lookup and data transfer operations when processing each 32-bit machine word. To enhance the compression and decompression performance of Simple-9 algorithm, we propose a successive storage structure and processing metric to compress two successive Simple-9 encoded sequence of integers in a single data processing procedure, thus the name Successive Simple-9 (SSimple-9). In essence, the algorithm shortens the process of branch operations, table lookup and data transfer operations when compressing the integer sequence. More precisely, we initially present the data storage format and mask table of SSimple-9 algorithm. Then, for each mode in the mask table, we design and hard-code the main steps of the compression and decompression processes. Finally, analysis and comparison on the experimental results of the simulation and TREC datasets show the compression and decompression efficiency speedup of the proposed SSimple-9 algorithm.

This paper presents the design and experimental evaluation of 60GHz small cell radio access based on IEEE 802.11ad/WiGig. The access point (AP) prototype used combines three RF modules with beamforming technology to provide 360° area coverage. In order to compensate for limited communication distance, multiple APs are employed to achieve wide area coverage. A handover algorithm suitable for IEEE 802.11ad/WiGig is employed to achieve flexible control of the cell coverage of each AP. As a proof of concept, a prototype system is set up at Narita International Airport and the capability of multiuser Gb/s wireless access is successfully demonstrated. In addition, the system behavior under stringent conditions is evaluated by load testing and throughput degradation due to co-channel and inter-channel interference is investigated.

Object detection is at the heart of nearly all the computer vision systems. Standard off-the-shelf embedded processors are hard to meet the trade-offs among performance, power consumption and flexibility required by object detection applications. Therefore, this paper presents an Application Specific Instruction set Processor (ASIP) for object detection using AdaBoost-based learning algorithm with Haar-like features as weak classifiers. Algorithm optimizations are employed to reduce memory bandwidth requirements without losing reliability. In the proposed ASIP, Single Instruction Multiple Data (SIMD) architecture is adopted for fully exploiting data-level parallelism inherent to the target algorithm. With adding pipeline stages, application-specific hardware components and custom instructions, the AdaBoost algorithm is accelerated by a factor of 13.7x compared to the optimized pure software implementation. Compared with ARM946 and TMS320C64+, our ASIP shows 32x and 7x better throughput, 10x and 224x better area efficiency, 6.8x and 18.8x better power efficiency, respectively. Furthermore, compared to hard-wired designs, evaluation results show an advantage of the proposed architecture in terms of chip area efficiency while maintain a reliable performance and achieve real-time object detection at 32fps on VGA video.