This paper studies the simple dynamic binary neural network characterized by the signum activation function, ternary weighting parameters and integer threshold parameters. The network can be regarded as a digital version of the recurrent neural network and can output a variety of binary periodic orbits. The network dynamics can be simplified into a return map, from a set of lattice points, to itself. In order to store a desired periodic orbit, we present two learning algorithms based on the correlation learning and the genetic algorithm. The algorithms are applied to three examples: a periodic orbit corresponding to the switching signal of the dc-ac inverter and artificial periodic orbit. Using the return map, we have investigated the storage of the periodic orbits and stability of the stored periodic orbits.

To decrease memory access of the decoder for double binary convolutional turbo code (DB CTC), an iterative decoding scheme is proposed. Instead of accessing all of the backward state metrics from the state metric cache (SMC), a part of them is computed by the recalculation unit (RU) in the forward direction. By analysis and simulations, both the amount of memory access and the size of SMC are reduced by about 45%. Moreover, combined with the scaling technique, the proposed scheme gets decoding performance near to that of the well-known Log-MAP algorithm.

In this paper, we present new important privacy goals for on-line matchmaking protocols, which are resistance to off-line dictionary attacks and forward privacy of users' identities and matching wishes. We enhance traditional privacy requirements (e.g., user anonymity, matching-wish authenticity) with our new privacy goals and define the notion of privacy-enhanced matchmaking. We show that previous solutions for on-line matchmaking do not satisfy the new privacy goals and argue that privacy-enhanced matchmaking cannot be provided by solutions to seemingly related problems such as secret handshakes, set intersection, and trust negotiation. We define an adversary model, which captures the key security properties of privacy-enhanced matchmaking, and show that a simple, practical protocol derived by a two-step transformation of a password-based authenticated key exchange counters adversary attacks in a provable manner (in the standard model of cryptographic security).

We have optimized and evaluated organic thin-film solar cell devices with a structure of graded junction. The graded junction consisting of donor and accepter materials was fabricated by varying the deposition rates of both materials with a continuous grading, using two evaporation sources of cupper phthalocyanine and fullerene as p- and n-type materials, respectively. By evaluating device characteristics, optimized device structure ITO/CuPc (10 nm)/graded layer (35 nm)/C60 (15 nm)/BCP (10 nm)/Ag (100 nm) with an efficiency of 1.36% was obtained. In the structure, short-circuit current density was the largest and existence of larger voltage dependence in current density was observed. In addition, we have measured temperature dependences of current density versus voltage characteristics in the graded organic solar cell under illumination. The carrier extraction was enhanced by changing voltage possibly due to the internal electric field of the graded junction.

To provide robust wireless data transmission over fading channels, various schemes which involve the use of relays have been proposed. In some of those schemes, the relay chooses not to forward the received message if its reliability is deemed as too low. Some researchers refer to such schemes as selective decode-and-forward. Our work in this paper falls into such a category. More specifically speaking, the relay in our system is a censorial relay (a relay that performs censorial task). It evaluates the reliability, in terms of log likelihood ratio (LLR), of a received data bit (from the source). If its LLR magnitude is below some preset threshold, then it is censored (i.e. not sent to the destination). When the channel is Rayleigh faded, closed-form bit error rate (BER) expressions for the proposed system are derived for several scenarios. Those scenarios are differentiated by the availability of an energy detector (ED) and the various degrees of knowledge regarding the channel state information (CSI). Aided by those closed-form BER expressions, the system parameters can be efficiently optimized to achieve the minimum BER. Simulation results are observed to closely match theoretical values, as computed by the afore-mentioned closed-form BER expressions. As compared to some existing relay-assisted systems in which censoring is incorporated, the performance of our system is better in terms of BER when the same amount of CSI is exploited.

We implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.

The purpose of this study is to estimate the noise level of every pixel in a single noisy image, that is superimposed independent and non-identically distributed random variables with normal distribution. The method makes a set of similar pixels in the local region to the interest pixel using the approximate function of noise variance, and estimates with regard to the noise level. As the results show, the proposed method is effective in estimation of noise level of every pixel for any images.

A mixed storage-type design using flip-flops and latches (FF/latch-based design) has advantages on such as area and power compared to single storage-type design (only flip-flops or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. One of the fundamental aspects in FF/latch-based design is that different resource binding solutions could lead to the different numbers of latch-replacable registers. Therefore, as a first step, this paper addresses a datapath design problem in which resource binding and selecting storage-types of registers are simultaneously optimized for datapath area minimization (i.e., latch replacement maximization). An efficient algorithm based on the compatibility path decomposition and an integer linear programming-based exact approach are presented. Experiments confirm the effectiveness of the proposed approaches.

This paper proposes a novel high-temperature superconducting dual-band bandpass filter (HTS-DBPF), that employs a broadside coupling structure, in which quarter-wavelength resonators are formed on opposite sides of each substrate. This structure provides a dual-band operation of the BPF and flexibility, in the sense of having a wide range in selecting two center passband frequencies of the HTS-DBPF. This paper employs the ratio of the lower and higher center passband frequencies, α, as a criterion for evaluating the flexibility. The obtained α ranges are from 1 to 4.7, which are the widest for DBPFs for mobile communications applications, to the best knowledge of the authors. This paper presents a 2.4-/2.9-GHz band HTS-DBPF, as an experimental example, using a YBCO film deposited on an MgO substrate. The measured frequency responses of the HTS-DBPF agree with the electromagnetic simulated results. Measurement and simulation results confirm that the proposed filter architecture is effective in configuring a DBPF that can set each center passband frequency widely.

In this paper, we further study linear network error correction code on a multicast network and attempt to establish a connection between linear network error correction codes and representable matroids. We propose a similar but more accurate definition of matroidal error correction network which has been introduced by K. Prasad et al. Moreover, we extend this concept to a more general situation when the given linear network error correction codes have different error correcting capacity at different sinks. More importantly, using a different method, we show that a multicast error correction network is scalar-linearly solvable if and only if it is a matroidal error correction network.

We have proposed a method of identifying superspreaders by flow sampling and a method of filtering legitimate hosts from the identified superspreaders using a white list. However, the problem of how to optimally set parameters of φ, the measurement period length, m*, the identification threshold of the flow count m within φ, and H*, the identification probability for hosts with m=m*, remained unsolved. These three parameters seriously impact the ability to identify the spread of infection. Our contributions in this work are two-fold: (1) we propose a method of optimally designing these three parameters to satisfy the condition that the ratio of the number of active worm-infected hosts divided by the number of all vulnerable hosts is bound by a given upper-limit during the time T required to develop a patch or an anti-worm vaccine, and (2) the proposed method can optimize the identification accuracy of worm-infected hosts by maximally using a limited amount of memory resource of monitors.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

Petri nets are a kind of formal language that are widely applied in concurrent systems associated with resource allocation due to their abilities of the natural description on resource allocation and the precise characterization on deadlock. Weighted System of Simple Sequential Processes with Resources (WS3PR) is an important subclass of Petri nets that can model many resource allocation systems in which 1) multiple processes may run in parallel and 2) each execution step of each process may use multiple units from a single resource type but cannot use multiple resource types. We first prove that the liveness problem of WS3PR is co-NP-hard on the basis of the partition problem. Furthermore, we present a necessary and sufficient condition for the liveness of WS3PR based on two new concepts called Structurally Circular Wait (SCW) and Blocking Marking (BM), i.e., a WS3PR is live iff each SCW has no BM. A sufficient condition is also proposed to guarantee that an SCW has no BM. Additionally, we show some advantages of using SCW to analyze the deadlock problem compared to other siphon-based ones, and discuss the relation between SCW and siphon. These results are valuable to the further research on the deadlock prevention or avoidance for WS3PR.

In order to execute coherent Doppler processing in a high range-rate scenario, whether it is for detection, estimation or imaging, range walk embedded in target return should be compensated first. In case of a bistatic radar geometry where a transmitter, a receiver and a target can be all moving, the extent of range walk depends on their relative positions and velocities. This paper presents a coherent Doppler processing algorithm to achieve target detection and Doppler frequency estimation of a target under a bistatic radar geometry. This algorithm is based on the assumption that a target has constant Doppler frequency during a coherent processing interval (CPI). Thus, we first show under what condition the assumption could be valid. We next develop an algorithm, along with its implementation procedures where the region of range walk, called a window, is manipulated. Finally, the performance of a proposed algorithm is examined through simulations.

This paper proposes a method for evaluating visual differences caused by decimation. In many applications it is important to evaluate visual differences of two different images. There exist many image assessment methods that utilize the model of the human visual system (HVS), such as the visual difference predictor (VDP) and the Sarnoff visual discrimination model. In this paper, we extend and elaborate on the conventional image assessment method for the purpose of evaluating the visual difference caused by the image decimation. Our method matches actual human evaluation more and requires less computational complexity than the conventional method.

In the next generation mobile network, the demand for high data rate transmission will require an increase in the transmission power if the current mobile cellular network architecture is used. Multihop networks are considered to be a key solution to this problem. However, a new resource allocation algorithm is also required for the new network architecture. In this paper, we propose a resource allocation scheme for a parallel relay 2-hop OFDMA virtual cellular network (VCN) which can be applied in a multiuser environment. We evaluate, by computer simulation, the ergodic channel capacity of the VCN using the proposed algorithm, and compare the results with those of the conventional single hop network (SHN). In addition, we analyze the effect of the location of the relay wireless ports on the ergodic channel capacity of the VCN. We also study the degree of fairness of the VCN, using the proposed scheme, compared with that of the SHN. For low transmission power, the simulation results show: a) the VCN can provide a better ergodic channel capacity and a better degree of fairness than the SHN, b) the distance ratio for which the ergodic channel capacity of the VCN is maximal can be found in the interval 0.20.3, c) the ergodic channel capacity of the VCN remains better than that of the SHN as the number of users increases, and d) as the distance between the relay WPs and the base station increases, the channel capacity of VCN approaches that of the SHN.

Multichannel MAC protocols with a single control channel in a cognitive radio ad hoc network (CRAN) suffer from the bottleneck problem. So a multichannel MAC protocol that can realize a virtual control channel on all available channels is preferred. Discontiguous-Orthogonal Frequency Division Multiplexing (D-OFDM) enables multiple data to be sent and received on discontiguous multiple channels. In this paper, we propose a new cooperative multichannel MAC (CM-MAC) protocol using D-OFDM in a CRAN. In the proposed CM-MAC protocol, a new approach utilizing multiple discontiguous control channels is presented and a remedy to tackle new collision types by the approach using D-OFDM is provided. The proposed mechanism mitigates the bottleneck problem of the protocol using single control channel, but does not need to share hopping patterns between a sender and a receiver. In addition, cooperative communications with relays reduce the time required to send the data of low-rate secondary users (SUs) by enabling relay SUs to relay the data of source SUs. The proposed CM-MAC protocol is shown to enhance throughput. Analysis and simulations indicate that throughput performance improves compared to the MAC protocol using the split phase control channel (SPCC) approach.

A plane coupler has been developed for a two-dimensional (2D) wireless power transmission. This coupler can construct a continuous wireless power transmission system for mobile devices due to its small, light characteristics. This coupler has two elements connected with a 2D waveguide sheet, and coupling capacitances between the elements and the sheet decrease the coupler size by reducing their resonance frequencies. A propagation loss of -10.0 dB is obtained using the small 0.025-λ2 coupler. Continuous operation of the mobile device is demonstrated by applying wireless power transmission to the 2D waveguide sheet with the small plane coupler.

The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.