An improved algorithm is developed for correcting the topographic impact on satellite imagery. First, we analyze the topography induced distortion on satellite image. It is shown that the variation of aspect can cause the obvious different distortions in the remotely sensed image, and also effect the image illumination significantly. Because the illumination is the basis for topographic correction algorithms, we consider its variation in different sun-facing aspects in calculation a correction parameter and take it as a key element in the modified correction algorithm. Then, we apply the modified correction method on the actual Landsat Thematic Mapper satellite image. The topographic correction was done in different image data with different season and different solar angle. The corrected results show the effectiveness and accuracy using this approach.

In this paper, we propose a frequency domain active noise control (ANC) system without a secondary path model. The proposed system is based on the frequency domain simultaneous perturbation (FDSP) method we have proposed. In this system, the coefficients of the adaptive filter are updated only by error signals. The conventional ANC system using the filtered-x algorithm becomes unstable due to the error between the secondary path, from secondary source to error sensor, and its model. In contrast, the proposed ANC system has the advantage not to use the model. In this paper, we show the principle of the proposed ANC system, and examine its efficiency through computer simulations.

Synthetic aperture radar interferometry have been established in the past two decades, and used extensively for many applications including topographic mapping of terrain and surface deformation. Vegetation analysis is also a growing area of its application. In this paper, we propose an polarimetric SAR interferometry technique for interferometric phase extraction of each local scatterer. The estimated position of local scattering centers has an important information for effective tree height estimation of forest. The proposed method formulated for local scattering center extraction is based on the ESPRIT algorithm which is known for high-resolution capability of closely located incident waves. The method shows high-resolution performance when local scattered waves are uncorrelated and have different polarization characteristics. Using the method, the number of dominant local scattering centers and interferometric phases in each image pixel can be estimated directly. Validity of the algorithm is demonstrated by using examples derived from SIR-C data.

We present a simple cell scheduling algorithm for an input buffered switch. The suggested algorithm is based on iSLIP and consists of request, grant and accept steps. The pointer update scheme of iSLIP is simplified in the suggested algorithm. By virtue of the new update scheme, the performance of the suggested algorithm is better than that of iSLIP with one iteration. Using computer simulations under a uniform traffic, we show the suggested algorithm is more appropriate than iSLIP for scheduling of an input buffered switch with multiple service classes.

A plasma display panel (PDP) represents gray levels by the pulse number modulation technique that results in undesirable dynamic false contours on moving images. Among the various techniques proposed for the reduction of dynamic false contours, the optimization of the subfield pattern can be most easily implemented without the need for any additional dedicated hardware or software. In this paper, a systematic method for selecting the optimum subfield pattern is presented. In the proposed method, a subfield pattern that minimizes the quantitative measure of the dynamic false contour on the predefined test image is selected as the optimum pattern. The selection is made by repetitive calculations based on a genetic algorithm. Quantitative measure of the dynamic false contour calculated by simulation on the test image serves as a criterion for minimization by the genetic algorithm. In order to utilize the genetic algorithm, a structure of a string is proposed to satisfy the requirements for the subfield pattern. Also, three genetic operators for optimization, reproduction, crossover, and mutation, are specially designed for the selection of the optimum subfield pattern.

We propose the kernel-based pattern recognition hardware and its design methodology using the genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.

This paper proposes the Vector Evaluated GA-ICT (VEGA-ICT), a novel design method that employs the Genetic Algorithm (GA) to obtain the optimum antenna design. GA-ICT incorporates an arbitrary wire-grid model antenna to derive the optimum solution without any basic structure or limitation on the number of elements by merely optimizing an objective function. GA-ICT comprises the GA and an analysis method, the Improved Circuit Theory (ICT), with the following characteristics. (1) To achieve optimization of an arbitrary wire-grid model antenna without a basic antenna structure, the unknowns of the ICT are directly assigned to variables of the GA in the GA-ICT. (2) To achieve a variable number of elements, duplicate elements generated by using the same feasible region are deleted in the ICT. (3) To satisfy all complex design conditions, the GA-ICT generates an objective function using a weighting function generated based on electrical characteristics, antenna configuration, and size. (4) To overcome the difficulty of convergence caused by the nonlinearity of each term in the objective function, GA-ICT adopts a vector evaluation method. In this paper, the novel GA-ICT method is applied to downsize sector antennas. The calculation region in GA-ICT is reduced by adopting cylindrical coordinates and a periodic imaging structure. The GA-ICT achieves a 30% reduction in size compared to the previously reported small sector antenna, MS-MPYA, while retaining almost the same characteristics.

First, we give a graph-theoretic formalization for the spare assignment problems for two cases of reconfiguring NN mesh-connected processor arrays with spares on a diagonal line in the array or two orthogonal lines at the edges of the array. Second, we discuss the problems for minimizing the numbers of "dangerous processors" for the cases. Here, a dangerous processor is a nonfaulty one for which there remains no spare processor to be assigned if it becomes faulty, without modifying the spare assignments to other faulty processors. The problem for the latter case, originally presented by Melhem, has already been discussed and solved by the O(N2) algorithm in [3], but it's procedure is very complicated. Using the above graph-theoretic formalization, we give efficient plain algorithms for minimizing the numbers of dangerous processors by which the problems for both the cases can be solved in O(N) time.

This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

An optimal allocation model for the sub-processing-element (sub-PE) level redundancy is developed, which is solved by the genetic algorithms. In the allocation model, the average defect density D and the parameter δ are also considered in order to accurately analyze the element yield, where δ is defined as the ratio of the support circuit area to the total area of a PE. When the PE's area is imposed on the constraint, the optimal solutions of the model with different D and δ are calculated. The simulation results indicate that, for any fixed average defect density D, both the number of the optimal redundant sub-circuit added into a PE and the PE's yield decrease as δ increases. Moreover, for any fixed parameter δ, the number of the optimal redundant sub-circuit increases, while the optimal yield of the PE decreases, as D increases.

In this paper we present two contributions for a set of local transformations (a selection set) to improve a performance of a very large circuit. The first contribution is an idea of "padding node" and "multi-separator-set. " We have proven that combination of padding node and multi-separator-set provides the optimum selection set. The second contribution is our heuristic method to find a semi-optimum multi-separator-set, which uses a network flow algorithm. Our method is robust for very large circuits, because its memory usage and calculation time are linear and polynomial order with the size of the circuit. We have compared our method with Singh's selection function method, which provides the optimum selection set and is the best method in literature to date. Our method has successfully optimized delays of all circuits, while Singh's selection function method has aborted with three large circuits because of memory overflow. The results also has shown our method has a comparable capability in delay optimization to Singh's method, although our method is heuristic.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

This paper presents a new framework for synthesizing look-up table (LUT) networks. Some of the existing LUT network synthesis methods are based on one or two functional (Boolean) decompositions. Our method also uses functional decompositions, but we try to use various decomposition methods, which include algebraic decompositions. Therefore, this method can be thought of as a general framework for synthesizing LUT networks by integrating various decomposition methods. We use a cost database file which is a unique characteristic in our method. We also present comparisons between our method and some well-known LUT network synthesis methods, and evaluate the final results after placement and routing. Although our method is rather heuristic in nature, the experimental results are encouraging.

This paper proposes a non-linear adaptive algorithm, the amplitude banded RLS (ABRLS) algorithm, as an adaptation procedure for time variant channel equalizers. In the ABRLS algorithm, a coefficient matrix is updated based on the amplitude level of the received sequence. To enhance the capability of tracking for the ABRLS algorithm, a parallel adaptation scheme is utilized which involves the structures of decision feedback equalizer (DFE). Computer simulations demonstrate that the novel ABRLS based equalizer provides a significant improvement relative to the conventional RLS DFE on a rapidly time variant communication channel.

In this paper, we propose the evolutionary algorithm-based reasoning system and its design methodology. In the proposed design methodology, reasoning rules behind the past cases in each task (in each case database) are extracted through genetic algorithms and are expressed as truth tables (we call them 'evolved truth tables'). Circuits for the reasoning systems are synthesized from the evolved truth tables. Parallelism in each task can be embedded directly in the circuits by the hardware implementation of the evolved truth tables, so that the high speed reasoning system with small or acceptable hardware size is achieved. We developed a prototype system using Xilinx Virtex FPGA chips and applied it to the gene boundary reasoning (GBR) and English pronunciation reasoning (EPR), which are very important practical tasks in the genome science and language processing field, respectively. The GBR and the EPR prototype systems are evaluated in terms of the reasoning accuracy, circuit size, and processing speed, and compared with the conventional approaches in the parallel AI and the artificial neural networks. Fault injection experiments are also carried out using the prototype system, and its high fault-tolerance, or graceful degradation against defective circuits that suits to the hardware implementation using wafer scale LSIs is demonstrated.

In this paper, we propose an approach to solve the power control issue in a DS-CDMA cellular system using genetic algorithms (GAs). The transmitter power control developed in this paper has been proven to be efficient to control co-channel interference, to increase bandwidth utilization and to balance the comprehensive services that are sharing among all the mobiles with attaining a common signal-to-interference ratio(SIR). Most of the previous studies have assumed that the transmitter power level is controlled in a constant domain under the assumption of uniform distribution of users in the coverage area or in a continuous domain. In this paper, the optimal centralized power control (CPC) vector is characterized and its optimal solution for CPC is presented using GAs in a large-scale DS-CDMA cellular system under the realistic context that means random allocation of active users in the entire coverage area. Emphasis is put on the balance of services and convergence rate by using GAs.

An improved arithmetic coding which provides an encoder with finite calculation precision for source sequences over a countable alphabet is presented. Conventional arithmetic coding theoretically has infinite precision for real variables. However any algorithm implemented on a computer has finite precision. This implies that conventional arithmetic codes can only encode sequences over a finite alphabet. The improved arithmetic coding presented here has a computational complexity which is roughly proportional to the length of the source sequence for a given source.

The sub-recursive least squares (sub-RLS) algorithm estimates the coefficients of adaptive filter under the least squares (LS) criterion, however, does not require the calculation of inverse matrix. The sub-RLS algorithm, based on the different principle from the RLS algorithm, still provides a convergence property similar to that of the RLS algorithm. This paper first rewrites the convergence condition of the sub-RLS algorithm, and then proves that the convergence property of the sub-RLS algorithm successively approximates that of the RLS algorithm on the convergence condition.

Before we gave a fast generalized minimum distance (GMD) decoding algorithm for one-point algebraic-geometry (AG) codes. In this paper, we propose another fast GMD decoding algorithm for these codes, where the present method includes an erasure deletion procedure while the past one uses an erasure addition procedure. Both methods find a minimal polynomial set of a given syndrome array, which is a candidate for an erasure-and-error locator polynomial set constrained with an erasure locator set of each size. Although both erasure addition and deletion GMD decoding algorithms have been established for one-dimensional algebraic codes such as RS codes, nothing but the erasure addition GMD decoding algorithm for multidimensional algebraic codes such as one-point AG codes have been given. The present erasure deletion GMD decoding algorithm is based on the Berlekamp-Massey-Sakata (BMS) algorithm from the standpoint of constrained multidimensional shift register synthesis. It is expected that both our past and present methods play a joint role in decoding for one-point AG codes up to the error correction bound.

We propose an encoding method for one-point algebraic geometry codes that usually requires less computation than the ordinary systematic encoder.