In this paper, we consider a stabilization problem for the cart-pendulum system based on discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. First, the continuous and discrete cart-pendulum systems are explained. We next propose a transformation method that converts a discrete-time input derived from the discrete-time optimal regulator theory into a continuous-time zero-order hold input, and carry out some simulations on stabilization of the cart-pendulum system by the transformation method. Then, we apply not only our proposed method but also existing methods to an experimental laboratory of the cart-pendulum system and perform some experiments in order to verify the availability of the proposed method.

3D Mesh segmentation has become an important research field in computer graphics during the past few decades. Many geometry based and semantic oriented approaches for 3D mesh segmentation has been presented. However, only a few algorithms based on Markov Random Field (MRF) has been presented for 3D object segmentation. In this letter, we present a definition of mesh segmentation according to the labeling problem. Inspired by the capability of MRF combining the geometric information and the topology information of a 3D mesh, we propose a novel 3D mesh segmentation model based on MRF and Graph Cuts. Experimental results show that our MRF-based schema achieves an effective segmentation.

In this paper, we propose two new falsification attacks against Wi-Fi Protected Access Temporal Key Integrity Protocol (WPA-TKIP). A previous realistic attack succeeds only for a network that supports IEEE 802.11e QoS features by both an access point (AP) and a client, and it has an execution time of 12–15 min, in which it recovers a message integrity code (MIC) key from an ARP packet. Our first attack reduces the execution time for recovering a MIC key. It can recover the MIC key within 7–8 min. Our second attack expands its targets that can be attacked. This attack focuses on a new vulnerability of QoS packet processing, and this vulnerability can remove the condition that the AP supports IEEE 802.11e. In addition, we discovered another vulnerability by which our attack succeeds under the condition that the chipset of the client supports IEEE 802.11e even if the client disables this standard through the OS. We demonstrate that chipsets developed by several kinds of vendors have the same vulnerability.

We introduce the distributed estimation of a random vector signal in wireless sensor networks that follow coherent multiple access channel model. We adopt the linear minimum mean squared error fusion rule. The problem of interest is to design linear coding matrices for those sensors in the network so as to minimize mean squared error of the estimated vector signal under a total power constraint. We show that the problem can be formulated as a convex optimization problem and we obtain closed form expressions of the coding matrices. Numerical results are used to illustrate the performance of the proposed method.

This paper proposes a utility function-based scheduling algorithm for integrated real-time and non-real-time services in long-term evolution systems. The proposed utility function satisfies the target dropping ratio of real-time users; it uses the delay constraint and increases the throughput of non-real-time users by scheduling real-time users together with non-real-time users. Simulation results show that the proposed scheduling algorithm significantly improves the throughput of non-real-time users without sacrificing the quality of service of real-time users.

We consider secure wireless communications, where a source is communicating to a destination in the presence of K (K > 1) eavesdroppers. The source and destination both are equipped with multiple antennas, while each eavesdropper has a single antenna. The source aims to maximize the communication rate to the destination, while concealing the message from all the eavesdroppers. Combined with selective diversity, we propose a heuristic secrecy transmission scheme where the multiple-input-multiple-output (MIMO) secrecy channel is simplified into a multiple-input-single-output (MISO) one with the highest orthogonality to the eavesdropper channels. Then convex optimization is applied to obtain the optimal transmit covariance matrix for this selected MISO secrecy channel. Numerical results are provided to illustrate the efficacy of the proposed scheme.

Nowadays, a user authentication is very important in network environments. For safe authentication, they came up with six essential conditions in earlier studies. And a variety of mechanisms is presented by research scientists. However, they could not achieve the PFS. Because, though all these schemes are assumed that the communication between a smart card and a host is safe, actually it is not. Therefore, in this paper, we will point out what the communication between a smart card and a host is not safe, and propose a new user authentication mechanism that can reach to the PFS. And also, an encryption algorithm is used about 45% less than earlier studies in our proposed scheme. Thus, we can say that enhance the efficiency.

To assess the performance of maximum-likelihood (ML) based Nakagami m parameter estimators, current methods rely on Monte Carlo simulation. In order to enable the analytical performance evaluation of ML-based m parameter estimators, we study the statistical properties of a parameter Δ, which is defined as the log-ratio of the arithmetic mean to the geometric mean for Nakagami-m fading power. Closed-form expressions are derived for the probability density function (PDF) of Δ. It is found that for large sample size, the PDF of Δ can be well approximated by a two-parameter Gamma PDF.

This letter focuses on the performance analysis on the Adaptive Sidelobe Blanker (ASB) detection algorithm in homogeneous environments, and provides closed summation expressions for Probability of Detection (PD) and Probability of False Alarm (PFA) rate in terms of hypergeometric function. The derived results are more powerful and effective than previous integral ones. Moreover, the framework can be modified to solve the the performance analysis problem involving in F or/and beta distributions. Several numerical evaluations of the convergence rate and computation time are provided and discussed.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

In this paper, we analyze the best relay selection scheme for the soft-decision-and-forward (SDF) cooperative networks with multiple relays. The term `best relay selection' implies that the relay having the largest end-to-end signal-to-noise ratio is selected to transmit in the second phase transmission. The approximate performances in terms of pairwise error probability (PEP) and bit error rate (BER) are analyzed and compared with the conventional multiple-relay transmission scheme where all the relays participate in the second phase transmission. Using the asymptotics of the Fox's H-function, the diversity orders of the best relay selection and conventional relay scheme for the SDF cooperative networks are derived. It is shown that both have the same full diversity order. The numerical results show that the best relay selection scheme outperforms the conventional one in terms of bit error rate.

This letter focuses on the design of selective receivers for homogeneous scenarios where a very small number of secondary data are available. To this end, at the design stage it is assumed that the cell under test (CUT) contains a fictitious signal orthogonal to the nominal steering vector under the null hypothesis; the clutter covariance matrix is modeled as a random matrix with an inverse complex Wishart distribution. Under the above assumptions, we devise two Bayesian detectors based on the GLRT criterion, both one-step and two-step. It is shown that the proposed detectors have the same detection structure as their non-Bayesian counterparts, substituting the colored diagonal sample covariance matrix (SCM) for the classic one. Finally, a performance assessment, conducted by Monte Carlo simulations, has shown that our detectors ensure better rejection capabilities of mismatched signals than the existing Bayesian detectors, at the price of a certain loss in terms of detection of matched signals.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

This paper considers the discrete model of the cart-pendulum system modeled by discrete mechanics, which is known as a good discretizing method for mechanical systems and has not been really applied to control theory. We first sum up basic concepts on discrete mechanics and discuss the explicitness of the linear approximation of the discrete Euler-Lagrange Equations. Next, the discrete cart-pendulum system is derived and analyzed from the viewpoint of solvability of implicit nonlinear control systems. We then show a control algorithm to stabilize the discrete cart-pendulum based on the discrete-time optimal regulator theory. Finally, some simulations are shown to demonstrate the effectiveness of the proposed algorithm.

In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

The evolution of Internet, the growth of Internet users and the new enabled technological capabilities place new requirements to form the Future Internet. Many features improvements and challenges were imposed to build a better Internet, including securing roaming of data and services over multiple administrative domains. In this research, we propose a multi-domain access control infrastructure to authenticate and authorize roaming users through the use of the Diameter protocol and EAP. The Diameter Protocol is a AAA protocol that solves the problems of previous AAA protocols such as RADIUS. The Diameter EAP Application is one of Diameter applications that extends the Diameter Base Protocol to support authentication using EAP. The contributions in this paper are: 1) first implementation of Diameter EAP Application, called DiamEAP, capable of practical authentication and authorization services in a multi-domain environment, 2) extensibility design capable of adding any new EAP methods, as loadable plugins, without modifying the main part, and 3) provision of EAP-TLS plugin as one of the most secure EAP methods. DiamEAP Server basic performances were evaluated and tested in a real multi-domain environment where 200 users attempted to access network using the EAP-TLS method during an event of 4 days. As evaluation results, the processing time of DiamEAP using the EAP-TLS plugin for authentication of 10 requests is about 20 ms while that for 400 requests/second is about 1.9 second. Evaluation and operation results show that DiamEAP is scalable and stable with the ability to handle more than 6 hundreds of authentication requests per second without any crashes. DiamEAP is supported by the AAA working group of the WIDE Project.

This paper examines the robust performance of a load torque observer for the position control of a surface-mounted permanent magnet synchronous motor (PMSM) under parameter uncertainties. The load torque observer has been widely employed to compensate for unknown slow-varying disturbances without explicit analysis on the robustness against parameter uncertainties. By using the singular perturbation theory this paper presents an analysis on the robust performance of the load torque observer based on the reduced-order estimator. As the observer poles are placed sufficiently left of the complex plane, the feedforward compensation with estimation can recover nominal system performance without parameter uncertainties and load torque disturbance. An example shows the performance of the load torque observer.

In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.