In this paper a high-performance copy network named PPCN is proposed for large scale ATM switching systems. The proposed copy network consists of multiple planes of the P2I Copy Networks(PCN) arranged in parallel. The PCN planes are designed based on the P2I multistage interconnection networks (MINs). A single PCN plane is itself a preliminary self-routing copy network which, however, is not a non-blocking one. A novel dispatcher is designed to dispatch input cells to the PCN planes such that no internal blocking nor output contention arises during the cell replication procedure and the offered load can be shared in an efficient way. The architecture of the PPCN provides flexibility for the maximum fanout for an input cells. In a PPCN system, the maximum fanout for an input cells is determined only by the number of interconnection stages within the PCN planes, independent of the input size of the system. The performance of the PPCN is studied under uniform traffic. It is shown that a small constant number of PCN planes are sufficient for a PPCN system to achieve an acceptable low overflow probability regardless of the system size. The hardware complexity of an N N PPCN is O(N log2 K) and the length of the routing tag is O(log2 K) bits, where K is the maximum fanout for an input cell. The storage complexity of the translation tables adopted in an N-inlet PPCN is O(N), which is much lower than that of the previously proposed ones.

The Available Bit Rate (ABR) service of Asynchronous Transfer Mode (ATM) networks employs explicit rate notification algorithms to ensure better and fair distribution of available bandwidth among contending sources. The Enhanced Proportional Rate Control Algorithm (EPRCA) is one of the explicit rate control algorithms recommended by the ATM forum. In this paper, we identify deficiencies and problems associated with EPRCA and show that these cause unfairness in bandwidth utilization by the contending sources. We propose modification in EPRCA and call it Modified Enhanced Proportional Rate Control Algorithm (EPRCAM). We will argue and show through simulation results that EPRCAM leads to better link utilization and fair bandwidth allocation among contending sources. In our simulation model, EPRCAM results in as high as 97. 8% link utilization without cell loss.

The small planar packaging (SPP) system described here can be combined with card-on-board (COB) packaging in high-speed asynchronous transfer mode (ATM) switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density, high packaging density and high cooling capability. Prototype SPP system with air flow control structure for switching MCMs is constructed. Each MCM contained a 35 array of low thermal resistance butt-lead pin-grid-array on a glass ceramic substrate measuring 100170 mm with a plate fin heat-sink. This allows a power dissipation of more than 125 W per MCM, and 300 W per printed circuit board (PCB). Obtained board level heat flux density of the SPP system is 0. 37 W/cm2, which is six times that of conventional COB packaging. The SPP system combined with the COB packaging provides a small system foot-print and compact hardware for high-speed, large capacity ATM switching systems. This high-performance air cooling technology will be especially useful for future broadband ISDN high-speed switching systems.

An innovative small planar packaging(SPP)system is described that can be combined with card-on-board(COB)packaging in high-speed asynchronous transfer mode switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density and high packaging density, combining the advantages of both planar packaging used in computer systems and COB packaging used in telecommunication systems. Using a newly developed quasi-coaxial zero-insertion-force connector, point-to-point 311 Mb/s of 8-bit parallel signal transmission is achieved in an arbitrary location on the SPP systems shelf. Also about 5400 I/O connections in the region of the planar packaging system are made, thus the SPP system effectively eliminates the I/O pin count limitation. Furthermore, the heat flux management capability of the SPP system is five times higher than of conventional COB packaging because of its air flow control structure. An SPP system can easily enlarge the switch throughput and it will be useful for future high-speed, high-throughput ATM switching systems.

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

This paper introduces and studies the performance of an NN space-division, single-stage ATM switch with dual input-queueing. Each input port has two separate FIFO queues, an "odd" and an "even" queue. An incoming cell is stored at the input at either of two FIFOs according its output port destination (output ports are also labeled as "odd" or "even"). Hence we call this scheme the Odd-Even switch. We compare the Odd-Even switch to the ordinary input-buffered switch and we find that it can achieve a remarkably higher performance, in terms of throughput, mean delay and cell loss. This is due to the fact that the Head-of-Line effect becomes less problematic under the Odd-Even switch. Our results are based on various traffic models. Finally, we compare the Odd-Even scheme to the Look-ahead (input "window") policy.

Multicasting is an important feature for any switching network being intended to support broadband integrated services digital networks (B-ISDN). This paper proposes an improved multicast packet switch based on Lee's nonblocking copy network. The improved design retains the desirable features of Lee's network including its nonblocking property while adopting techniques to overcome the various limitations mentioned in various literature. The proposed network architecture utilizes d-dilated banyan networks to increase the amount of cells that can be replicated within the copy network. Cell splitting is used to optimize the utilization of the network's available bandwidth. Furthermore, the proposed architecture allows for the modular expansion in capacity to accomodate changing traffic patterns. The modular design of the proposed switch likewise offers easy handling and replacement of faulty modules.

The paper is focused on the architectural and technological solutions that will allow the transition from small to huge capacity ATM Switching Systems. This path starts from the industrial nodes available today and will arrive at the photonic switching architecture. The progressive introduction of photonics has already started with the use of optical interconnections in ATM nodes of hundreds of Gbit/s. A balanced use of microelectronics and photonics is the correct answer to the Terabit/s switching system challenge. After presenting a modular ATM Switching System, some technological solutions like Multichip Modules and Optical Interconnections are presented in order to explain how node capacity can be expanded. Some results of the research activity on photonic Switching are finally shown in order to exploit the great attitude of this technique to obtain very high throughput nodes.

Most of the existing analytical models for multistage ATM switching fabric are not accurate in the presence of a non-uniform traffic at the input of the switch. In this paper, we discuss the issues in modeling a multistage ATM switching fabric, and investigate the effect of independence assumptions in two previous analytical models. A highly accurate 4-state Markov chain model for evaluating the performance of ATM switching fabrics based on multistage switches with 22 finite output-buffered SEs is proposed. The proposed model correctly reflects the correlation of cell movements between two subsequent cycles and states of the buffers of two adjacent stages. By comparing the results obtained from the oroposed model, existing models and simulations, it has been shown that the proposed model is much more accurate than existing models in the presence of a non-uniform traffic in the switch. The results from the existing models are unsatisfactory in the presence of an increased blocking in the switch arising from a non-uniform traffic in the switch. On the contrary, the proposed model is very robust even under severe blocking in the switch.

Optical switching networks to transport vast amounts of information are important for B-ISDN services. The wavelength division multiplexing (WDM) is emerging as the dominant technology for future optical networks. This paper proposes a large capacity photonic ATM switch architecture using WDM technology. The switch consists of two stages. The first stage is a space switch and the second stage is a wavelength switch. The proposed switch is suitable for WDM optical ATM networks, that is, an input and an output of the switch are wavelength-division-multiplexed. The switch can provide very large ATM cell switching capacity, for instance, 10Tbit/s, with reasonable complexity. The main switch module of the proposed switch has a simple architecture, and reduces the amount of a buffer hardware by introducing the WDM concept.

Optical switching networks to transport vast amounts of information are important for B-ISDN services. Wavelength division multiplexing (WDM) is emerging as the dominant technology for future optical networks. A large capacity photonic ATM switch architecture using WDM technology is proposed in this paper. The proposed switch is suitable for WDM optical ATM networks, that is, an input and an output of the switch are wavelength division multiplexed. The basic switch module of the proposed switch has a simple architecture, and reduces the amount of a buffer hardware by introducing the WDM concept.

The optical ATM transport networks are the key technology for B-ISDN which integrates wide variety of communication services. In a photonic ATM switch, electronically operated switching control drastically limits the total throughput. With this bottleneck of the control speed of the switch compared to the cell transmission speed, if the unit of switching operation can be made longer, the system throughput will be improved. This paper proposes the optical backbone network configuration to obtain traffic concentrating effect to construct a large switching unit called a multi-cell. In the backbone network applied the concept of virtual path set (VPS), a multi-cell is constructed by cells from all of ATM switches in a regional network connected with each own's cross connect. The multi-cell format in the case of two different network models is investigated in this paper. The average delay and average idle cells per multi-cell in the multi-cell MUX of an optical cross connect are evaluated by computer simulation as the performance of the multi-cell transfer scheme in the backbone network. Simulation results show that the multi-cell transfer scheme can be operated efficiently with traffic load of more than 0.5. This paper also proposes the configuration of multiplexing and demultiplexing module to assemble and disassemble the multi-cell.

The modular and growable photonic ATM switch architecture described in this paper uses both time-division and wavelength-division multiplexing technologies, so the switch capacity can be expanded in both the time and frequency domains. It uses a new implementation of output buffering scheme that overcomes the bottleneck in receiving and storing concurrent ultra fast optical cells. The capacity in one stage of a switch with this architecture can be increased from 32 gigabits per second to several terabits per second in a modular fashion. The proposed switch structure with output channel grouping can greatly reduce the amount of hardware and still guarantee the cell sequence.

As promising copy networks of very large multicast switching networks for Broadband ISDN, multi-stage Recursive Copy Networks (RCN) have been proposed recently. In the multicast switch structure, the RCN precedes a point-to-point switch. At an RCN, all the copies of a master cell are generated recursively, i.e., a few copies of the master cell are made initially, and by considering each of these copies to be master cells, more copies are made which, in turn, are again considered to be master cells to make still more copies, the process thus progressing recursively till all the required copies are made. By this principle of recursive generation of copies, the number of copies that can be generated is independent of the hardware size of the RCN. A limitation of RCNs is that buffer sizes at all stages except the first stage have to be large so as to keep the cell loss due to buffer overflow within desired limits. This paper inspects a flow control scheme by which the probability of buffer overflow can be kept low, even though the buffer sizes at later stages are not large. Under this flow control procedure, a cell is not transmitted from a stage to the succeeding stage, if the occupancy level of the buffer of the succeeding stage exceeds a threshold. We study by simulation the performance aspects of such a flow control scheme in RCNs under cut-through switching scheme and under store-and-forward switching scheme. At high load intensities, the overflow probability can be reduced by an order of magnitude in 2-stage RCNs and by two orders of magnitude in 3-stage RCNs. To restrict the overflow probability within a given limit, the required buffer size is less under flow control than under no flow control. The implementation of the flow control is simple and the control overhead is small, thereby making the scheme attractive for implementation in high speed switching environments. Further, the proposed flow control scheme does not disturb the cell sequence.