We propose a scheme by which Broadcast Satellite/Communication Satellite- radio frequency (BS/CS-RF) converted TV signals are transmitted over optical fiber, and also propose a simultaneous Frequency Modulation (FM) converted CATV and BS/CS-RF converted TV optical transmission system as one of its applications. To confirm the proposals, we demonstrate the simultaneous transport of FM converted CATV signals and BS/CS-RF converted TV signals over a single optical fiber. In the experiments, 40 carriers of AM-VSB CATV channels, 30 carriers of 64-QAM digital TV channels, 8 carriers of FM/TC8PSK BS-TV channels, and 12 carriers of QPSK CS-TV channels are simultaneously transmitted. For optical access network application, the practical transmission length of 15 km over 1.3 µm-zero-dispersion optical fiber can be achieved by using dispersion compensation fiber (DCF).

A novel pitch-synchronous auditory-based feature extraction method for robust automatic speech recognition (ASR) is proposed. A pitch-synchronous zero-crossing peak-amplitude (PS-ZCPA)-based feature extraction method was proposed previously and it showed improved performances except when modulation enhancement was integrated with Wiener filter (WF)-based noise reduction and auditory masking. However, since zero-crossing is not an auditory event, we propose a new pitch-synchronous peak-amplitude (PS-PA)-based method to render the feature extractor of ASR more auditory-like. We also examine the effects of WF-based noise reduction, modulation enhancement, and auditory masking in the proposed PS-PA method using the Aurora-2J database. The experimental results show superiority of the proposed method over the PS-ZCPA and other conventional methods. Furthermore, the problem due to the reconstruction of zero-crossings from a modulated envelope is eliminated. The experimental results also show the superiority of PS over PA in terms of the robustness of ASR, though PS and PA lead to significant improvement when applied together.

A hard real-time system is one whose correctness depends not only on the logical result, but also when the results are produced. While many techniques have been proposed for single processor real-time systems, multiprocessor systems have not been studied so extensively. In this paper, we mainly propose two variant (DCTS) by using the Early-Release-Fair (ERfair) and Proportionate-fair (Pfair) model with integral assumptions for identical multi-processor real-time systems. ERfair is a scheduling model for real-time tasks on a multiprocessor system. On the different definitions of distance constraint, we propose two efficient scheduling algorithms designed to probe whether the distance constraints of all ER-fair tasks can be guaranteed. If the distance constraints cannot be guaranteed, then the proposed algorithms gather the unfeasible tasks and inflate them with a reweighting function. The proposed algorithms are linear-time and most suitable for dynamic systems. The experimental results reveal that the proposed algorithms increase significantly the ratio of schedulable task sets.

In this letter, a blind frequency offset estimation algorithm is proposed for OFDM systems. The proposed method exploits the intrinsic phase shift between neighboring samples in a single OFDM symbol, incurred by a frequency offset. The proposed algorithm minimizes a novel cost function, which is the squared error of the candidate frequency offset compensated signals from two different observation windows. Also, the solution of the proposed algorithm is given by an explicit equation, which does not require any iterative calculation. It is shown that the performance of the proposed method is better than those of the conventional methods, especially in the presence of multipath channels. This is due to the fact that the proposed method is insensitive to inter-symbol interference (ISI).

Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome [1]-[5]. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (Vdd_min) for the write operation even if considering a sufficiently-large random threshold voltage (Vth) variations. The following points have been shown based on an actual 65 nm CMOS device variation data and the implemented layout data that 1) Vdd_min for the write operation can be lowered from Vdd=1.1 V down to 0.8 V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes [1],[2] at Vdd=0.7 V and 1.0 V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/Vdd) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes [1],[2] at Vdd=0.75 V and 1.0 V, respectively. As an actual implementation in a 65 nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.

This paper introduces a common database, an evaluation framework, and its baseline recognition results for in-car speech recognition, CENSREC-3, as an outcome of the IPSJ-SIG SLP Noisy Speech Recognition Evaluation Working Group. CENSREC-3, which is a sequel to AURORA-2J, has been designed as the evaluation framework of isolated word recognition in real car-driving environments. Speech data were collected using two microphones, a close-talking microphone and a hands-free microphone, under 16 carefully controlled driving conditions, i.e., combinations of three car speeds and six car conditions. CENSREC-3 provides six evaluation environments designed using speech data collected in these conditions.

This paper deals with computation of parallel degree, PARAdeg, for (dataflow) program nets with SWITCH-nodes. Ge et al. have given the definition of PARAdeg and an algorithm of computing PARAdeg for program nets with no SWITCH-nodes. However, for program nets with SWITCH-nodes, any algorithm of computing PARAdeg has not been proposed. We first show that it is intractable to compute PARAdeg for program nets with SWITCH-nodes. To do this, we define a subclass of program nets with SWITCH-nodes, named structured program nets, and then show that the decision problem related to compute PARAdeg for acyclic structured program nets is NP-complete. Next, we give a heuristic algorithm to compute PARAdeg for acyclic structured program nets. Finally, we do experiments to evaluate our heuristic algorithm for 200 acyclic structured program nets. We can say that the heuristic algorithm is reasonable, because its accuracy is more than 96% and the computation time can be greatly reduced.

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

Petri nets have recently become widely accepted as a description method for biological pathways by researchers in computer science as well as those in biology. This paper gives an overview of Petri net formalisms to describe biological pathways and discusses their use in modelings and simulations for the systematic understandings of biological pathways. After reviewing the use of various types of Petri nets for the biological pathway modelings, we showed the examples that analyze fundamental properties of biological pathways using T-invariant, P-invariant, siphon, and trap. Applications of hybrid Petri nets for producing new biological hypotheses through simulations are also illustrated.

Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.

A family of sequences with zero correlation zone, which is shortly called a ZCZ set, can provide CDMA system without co-channel interference nor influence of multipath. This paper presents two types of ZCZ sets of non-binary sequence pairs, which achieve the upper bound of family size for length and zero correlation zone. One, which is produced by use of a perfect complementary pair and an orthogonal code, can change zero correlation zone, while the upper bound is kept. The other, which is generated by use of a newly defined orthogonal pair and an orthogonal code, can offer such CDMA system as a binary ZCZ set seems to be used.

Currently, multiband orthogonal frequency division multiplexing (MB-OFDM) is considered to be one of the modulation schemes of UWB and is being actively investigated. It is necessary to provide low-cost receivers for consumers to receive wide support for the MB-OFDM system. Such receivers can be achieved by utilizing direct-conversion architecture. Direct-conversion architecture suffers from IQ imbalance. IQ imbalance causes intercarrier interference (ICI) in the demodulated signals. In this paper, a new scheme of IQ imbalance compensation using transmit diversity is proposed. This scheme enables the system to achieve frequency diversity and simultaneously compensates for the influence of IQ imbalance. It is shown that the performance of the proposed scheme is better than that of the conventional IQ imbalance compensation scheme.

Orthogonal Frequency Division Multiplexing (OFDM) systems are very sensitive to the frequency offset of the local oscillator at the receiver while the symbol timing offset can be absorbed in the guard interval. For the same reason, estimation of the frequency characteristics, needed for OFDM to be adapted to the frequency selective fading, can only be carried out conventionally after the frequency offset has been compensated. And accurate estimation of large frequency offset certainly requires high precision estimate of the frequency characteristics. In this paper, we propose a new joint estimation method of the frequency offset and the channel frequency response using an Expectation-Maximization (EM) algorithm for OFDM systems. The proposed algorithm overcomes the limitation of the thus far proposed algorithm. By computer simulations, we show the proposed algorithm provides estimation accuracy close to its lower bound in a wide range of the frequency offset.

We developed an olfactory display to blend 8 component odors at any composition. The solenoid valves controlled by an algorithm with delta sigma modulation showed the sufficient capability. Then, we developed a system for presenting a movie together with scents. We actually made a movie with scents and evaluated it using questionnaire survey. It was found that the scene with smell attracted the experimental subjects' attention and, moreover, the contrast of the pleasant smell with the offensive one emphasized their attention. Furthermore, we established several guidelines for producing movies with scents.

In this paper, we evaluate the performance of asymmetric Time Division Duplex (TDD) system that employs Adaptive Modulation and Coding (AMC) and Hybrid ARQ, with consideration of the effect of control delays in TDD. Channel reciprocity characteristic in TDD allows utilization of open loop channel estimation to choose appropriate modulation and coding scheme (MCS) level for AMC. However, control delay in AMC and HARQ depends on TDD time slot allocation formats. Large control delay in AMC will result in false MCS selection due to the poor channel correlation between measured channel state from the received signals and instantaneous channel state of actual transmission with the MCS selected based on the measured channel state. We present an analytical approach to calculate the probability of MCS level selection error in different channel conditions for different asymmetric time slot allocations. From the theoretical and simulation results, it is shown that the instantaneous throughput per slot depends not only on maximum Doppler frequency but also on asymmetric slot allocations. Average delay time that yields error free packet reception in the downlink increases as the number of continuous downlink slots increases.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

A dynamically reconfigurable device is a device that can change its hardware configuration arbitrarily often in order to achieve the desired performance and functions. Since several tasks are executed on the device concurrently, scheduling of both task execution and reconfiguration is an important problem. In our model, the dynamically reconfigurable device is represented by a two-level hierarchical automaton, and execution of each periodic task is represented by a timed discrete event system. We propose a composition rule to get an automaton, which represents non-preemptive execution of periodic tasks on the dynamically reconfigurable device. We introduce a method to get a feasible execution sequence of tasks by using state feedback control.

We study computation of a controllable sublanguage of a given non-prefix-closed regular specification language for an unbounded Petri net. We approximate the generated language of the unbounded Petri net by a regular language, and compute the supremal controllable sublanguage of the specification language with respect to the regular language approximation. This computed language is a controllable sublanguage with respect to the original generated language of the unbounded Petri net, but is not necessarily the supremal one. We then present a sufficient condition under which the computed sublanguage is the supremal controllable sublanguage with respect to the original generated language of the unbounded Petri net.

In this paper, we present a scheduler that incorporates round robin service within a VirtualClock discipline. Time-stamp based scheduling algorithms attain a low local delay bound and performance guarantee, but are computationally complex. On the other hand, round robin schemes are simple to implement and have computational complexity of O(1), but they are well known for their output burstiness and short-term unfairness. In order to overcome this problem, we combine round robin with VirtualClock in an algorithm we call VCRR. VCRR possesses better fairness than simple round robin, low jitter and a good scheduling delay bound. At the same time, VCRR preserves the O(1) time complexity of round robin. Simulation experiments show VCRR's efficiency in terms of delay performance, jitter and fairness.

Recently, efficient algorithms have been proposed for finding all characteristic curves of one-port piecewise-linear (PWL) resistive circuits. Using these algorithms, a middle scale one-port circuit can be represented by a PWL resistor that is neither voltage nor current controlled. By modeling often used one-port subcircuits by such resistors (macromodels), large scale circuits can be analyzed efficiently. In this paper, an efficient method is proposed for finding DC operating points of nonlinear circuits containing such neither voltage nor current controlled resistors using the SPICE-oriented approach. The proposed method can be easily implemented on SPICE without programming.