This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-Vth CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

We investigated the use of AlOx:N/SiNy stacked gate dielectric as an alternate gate dielectric, which were prepared by alternately repeating sub-nanometer deposition of Al2O3 from an alkylamine-stabilized AlH3 + N2O gas mixture and rapid thermal nitridation in NH3. The negative fix charges, being characteristics of almina, were as many as 3.91012 cm-2 in the effective net charge density. The effective dielectric constant and the breakdown field were 8.9 and 8 MV/cm, respectively, being almost the same as pure Al2O3. And we have demonstrated that the leakage current through the AlOx:N/SiNy stacked gate dielectric with a capacitance equivalent thickness (CET) of 1.9 nm is about two orders of magnitude less than that of thermally-grown SiO2. Also, we have confirmed the dielectric degradation similar to the stress-induced leakage current (SILC) mode and subsequent soft breakdown (SBD) reported in ultrathin SiO2 under constant current stress and a good dielectric reliability comparable to thermally-grown ultrahin SiO2. From the analysis of n+poly-Si gate metal-insulator-semiconductor field effect transistor (MISFET) performance, remote coulomb scattering due to changes in the gate dielectric plays an important role on the mobility degradation of MISFET with AlON/SiON gate stack.

We propose a novel Schottky barrier diode with a dual Schottky structure combined with an AlGaN/GaN heterostructure. The purpose of this diode was to lower the on-state voltage and to maintain the high reverse breakdown voltage. An AlGaN/GaN heterostructure was grown using a metalorganic chemical vapor deposition (MOCVD). The Schottky barrier diode with a dual Schottky structure was fabricated on the AlGaN/GaN heterostructure. As a result, the on-voltage of the diode was below 0.1 V and the reverse breakdown voltage was over 350 V.

This paper describes a formal verification for a shared-memory-style communication system. We first describe two versions (i.e. abstract and concrete) of the communication system based on an I/O-automaton, which is a formal system for distributed algorithms. Then, we prove the concrete version can perform all the external operations of the abstract version. This result, together with a former result, leads to the equivalence of the two versions. The proof is done by Larch theorem prover, and is the ever largest case study using I/O-automata.

This paper provides algorithms in order to solve an interval implicit function of the Poincare map generated by a continuous piece-wise linear (CPWL) vector field, with the use of interval arithmetic. The algorithms are implemented with the use of MATLAB and INTLAB. We present an application to verification of canards in two-dimensional CPWL vector field appearing in nonlinear piecewise linear circuits frequently, and confirm that the algorithms are effective.

A memory address allocation method for digital signal processors of indirect addressing with indexed auto-modification is proposed. At first, address auto-modification amounts for a given program are analyzed. And then, address allocation of program variables are moved and shifted so that both indexed and simple auto-modifications are effectively exploited. For further reduction in overhead codes, a memory address allocation method coupled with computational reordering is proposed. The proposed methods are applied to the existing compiler, and generated codes prove their effectiveness.

Hypersequential programming is a new method of concurrent-program development in which the original concurrent program is first serialized, then tested and debugged as a set of sequential programs (scenarios), and finally restored into the target concurrent program by parallelization. Both high productivity and reliability are achieved by hypersequential programming because testing and debugging are done for the serialized versions and the correctness of the serialized programs is preserved during the subsequent parallelization. This paper proposes scenario-based hypersequential programming for reactive multitasking systems that have not only concurrency and nondeterminacy, but also interruption and priority. Petri nets with priority are used to model reactive systems featuring interruption and priority-based scheduling. How reactive systems are made highly reliable by this approach is explained and the effectiveness of the approach is demonstrated through the example of a telephone terminal control program.

This paper addresses the estimation of time delay between two spatially separated noisy signals by system identification modeling with the input and output corrupted by additive white Gaussian noise. The proposed method is based on a modified adaptive Butler-Cantoni equalizer that decouples noise variance estimation from channel estimation. The bias in time delay estimates that is induced by input noise is reduced by an IIR whitening filter whose coefficients are found by the Burg algorithm. For step time-variant delays, a dual mode operation scheme is adopted in which we define a normal operating (tracking) mode and an interrupt operating (optimization) mode. In the tracking mode, only a few coefficients of the impulse response vector are monitored through L1-normed finite forward differences tracking, while in the optimization mode, the time delay optimized. Simulation results confirm the superiority of the proposed approach at low signal-to-noise ratios.

Global computing system (GCS) harnesses the idle CPU resources of clients connected to Internet for solving large problems that require high volume of computing power. Since GCS scale to millions of clients, many projects usually adopt coarse-grained scheduling in order to reduce server-side contention at the expense of sacrificing the degree of parallelism and wasting CPU resources. In this paper, we propose a new type of client, i.e., a scheduling proxy that enables adaptive-grained scheduling between the server and clients. While the server allocates coarse-grained work units to scheduling proxies alone, clients download fine-grained work units from a relatively nearby scheduling proxy not from the distant server. By computation of small work units at client side, the turnaround time of work unit can be reduced and the waste of CPU time by timeout can be minimized without increasing the performance cost of contention at the server. In addition, in order not to lose results in the failure of scheduling proxies, we suggest a technique of result caching in clients.

Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.

This paper presents two new intelligent methods to linearize the Multi-Carrier Power Amplifiers (MCPA). One of the them is based on the Neuro-Fuzzy controller while the other uses two small neural networks as a polar predistorter. Neuro-Fuzzy controllers are not model based, and hence, have ability to control the nonlinear systems with undetermined parameters. Both methods are adaptive, low complex, and can be implemented in base-band part of the communication systems. The performance of the linearizers is obtained via simulation. The simulation is performed for three different scenarios; namely, a multi-carrier amplifier for GSM with four channels, a CDMA amplifier and a multi-carrier amplifier with two tones. The simulation results show that Neuro-Fuzzy Controller (NFC) and Neural Network Polar Predistorter (NNPP) have higher efficiencies so that reduce IMD3 by more than 42 and 32 dB, respectively. The practical implementation aspects of these methods are also discussed in this paper.

Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.

High-speed, area-efficient, and low-power Montgomery modular multipliers for RSA algorithm have been developed for digital signature and user authentication in high-speed network systems and smart card LSIs. The multiplier-accumulators (MAC) in the developed Montgomery modular multipliers have a non-identical multiplicand/multiplier word length organization. This organization can eliminate the bandwidth bottleneck associated with a data memory, and enables to use a single-port memory for area and power reductions. The developed MAC is faster than the conventional identical word length organization due to the shortened critical path. For smart card applications, an area-efficient architecture with 42 kgates can produce 1.2 digital signatures in a second for 2,048-bit key length with the power consumption of 6.8 mW.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

We extend the differential space time block code (STBC) using nonconstant modulus constellations of two transmit antennas to four transmit antennas case. The proposed method obtains larger minimum Euclidean distances than those of conventional differential STBC with PSK constellations. We derive the symbol error rate (SER) performance of the proposed method and demonstrate the SER performance using computer simulations for both static and fast fading channels. For transmission rates greater than 2 bits/channel use and 3 bits/channel use, the proposed method outperforms the conventional differential STBC.

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

This paper proposes a Voice Activity Detection (VAD) algorithm using Radial Basis Function (RBF) network. The k-means clustering and Least Mean Square (LMS) algorithm are used to update the RBF network to the underlying speech condition. The inputs for RBF are the three parameters a Code Excited Linear Prediction (CELP) coder, which works stably under various background noise levels. Adaptive hangover threshold applies in RBF-VAD for reducing error, because threshold value has trade off effect in VAD decision. The experimental results show that the proposed VAD algorithm achieves better performance than G.729 Annex B at any noise level.

This letter derives a new exact and general closed-form expression involving a two-dimensional joint Gaussian Q-function for the symbol error rate (SER) of M-ary Phase Shift Keying (MPSK) under an additive white Gaussian noise (AWGN) channel. By using two rotations of coordinates the correlation coefficient between two Gaussian random vectors is provided, then with the derived correlation coefficient that characterizes the two-dimensional joint Gaussian Q-function, a new expression for the SER of MPSK is presented. The derived new SER expression offers a convenient method to evaluate the performances of MPSK for various cases of practical interest.

This letter mathematically proves that the performance of the new protocol in Ref. [1] is better than that of the existing protocol. It was proposed that a frame from an access device is delivered over the access link and then it is multiplexed and packed into ATM cell at an access node and then the cell is carried toward a voice gateway, by using a method to split two sublayers in AAL2. That means one sublayer is implemented at the subscriber access device and the other sublayer is implemented at the access node. Access devices using the protocol achieve higher utilization of CID and waste fewer ATM resource per the access device. Mathematical analysis is performed on the proposed and existing protocol, and both upstream cell rate and padding probability are calculated. The proposed protocol shows lower upstream traffic rate and padding cell probability than the existing protocol.

Packet classification is important in fulfilling the requirements of differentiated services in next generation networks. One of interesting hardware solutions proposed to solve the packet classification problem is bit vector algorithm. Different from other hardware solutions such as ternary CAM, it efficiently utilizes the memories to achieve an excellent performance in medium size policy database; however, it exhibits poor worst-case performance with a potentially large number of policies. In this paper, we proposed an improved bit-vector algorithm named Condensate Bit Vector which can be adapted to large policy databases in the backbone network. Experiments showed that our proposed algorithm drastically improves in the storage requirements and search speed as compared to the original algorithm.