This paper presents two new intelligent methods to linearize the Multi-Carrier Power Amplifiers (MCPA). One of the them is based on the Neuro-Fuzzy controller while the other uses two small neural networks as a polar predistorter. Neuro-Fuzzy controllers are not model based, and hence, have ability to control the nonlinear systems with undetermined parameters. Both methods are adaptive, low complex, and can be implemented in base-band part of the communication systems. The performance of the linearizers is obtained via simulation. The simulation is performed for three different scenarios; namely, a multi-carrier amplifier for GSM with four channels, a CDMA amplifier and a multi-carrier amplifier with two tones. The simulation results show that Neuro-Fuzzy Controller (NFC) and Neural Network Polar Predistorter (NNPP) have higher efficiencies so that reduce IMD3 by more than 42 and 32 dB, respectively. The practical implementation aspects of these methods are also discussed in this paper.

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

We analyzed passivation film and the AlGaN surface states using open-gated structures of AlGaN/GaN HFETs by numerical simulation and experiments. From the analyses, we confirmed that insulating film conductivity plays the prominent roles in device performances of the wide bandgap semiconductor device. Device simulation confirmed that the difference in ID-VG characteristics is due to the trapping type of the surface states; electron-trap type or hole-trap type. For electron-trap type surface states, the surface potential pinned at electron quasi-Fermi level, which is the same as the channel potential in the open-gated FETs. As a result, surface potential of ungated region is equal to the channel electric potential resulting in the uncontrollability of the channel current by the edge placed gate electrode. For hole-trap type surface states, the surface potential is pinned at hole quasi-Fermi level, which must be the same as the edge placed gate electrode potential. Then, the AlGaN surface potential varies with the electrode potential variation allowing the control of channel current as if the whole channel is covered with a metal electrode. Experiments for open-gated FET with unpassivated surface show no current variation. This corresponds to electron-trap type surface states from the simulation. On the other hand, SiOX evaporated open-gated FET show current control by the gate electrode. The ID-VG characteristics resembles in simulated ID-VG characteristics with hole-trap surface states. However, the estimated time constants for the trap reactions are incredibly long due to the deep energy level for the surface states in wide bandgap semiconductors. In addition, the open-gated FET showed reverse threshold shift to the value expected from the hole-trap pinning levels. So, we concluded that the no current variation for the unpassivated open-gated FET can be attributed to electron traps in the surface states, but the control of the drain current for SiOX deposited open-gated FET is not by surface hole-traps, but by slightly conductive passivation film of SiOX.

This manuscript proposes an FPGA by embedding a multidimensional switch topology onto a two-dimensional chip. We show, using Rent's Rule, that this procedure reduces the number of switches. Then we propose the actual procedure and demonstrate that this does not increase metal wire density critically.

This paper proposes a Voice Activity Detection (VAD) algorithm using Radial Basis Function (RBF) network. The k-means clustering and Least Mean Square (LMS) algorithm are used to update the RBF network to the underlying speech condition. The inputs for RBF are the three parameters a Code Excited Linear Prediction (CELP) coder, which works stably under various background noise levels. Adaptive hangover threshold applies in RBF-VAD for reducing error, because threshold value has trade off effect in VAD decision. The experimental results show that the proposed VAD algorithm achieves better performance than G.729 Annex B at any noise level.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

This paper describes a formal verification for a shared-memory-style communication system. We first describe two versions (i.e. abstract and concrete) of the communication system based on an I/O-automaton, which is a formal system for distributed algorithms. Then, we prove the concrete version can perform all the external operations of the abstract version. This result, together with a former result, leads to the equivalence of the two versions. The proof is done by Larch theorem prover, and is the ever largest case study using I/O-automata.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.

We propose a novel Schottky barrier diode with a dual Schottky structure combined with an AlGaN/GaN heterostructure. The purpose of this diode was to lower the on-state voltage and to maintain the high reverse breakdown voltage. An AlGaN/GaN heterostructure was grown using a metalorganic chemical vapor deposition (MOCVD). The Schottky barrier diode with a dual Schottky structure was fabricated on the AlGaN/GaN heterostructure. As a result, the on-voltage of the diode was below 0.1 V and the reverse breakdown voltage was over 350 V.

Several regular topologies have been proposed to be used as the logical topology for WDM networks. These topologies are usually evaluated and compared based on the metrics related to network performance. It can be simply shown that this is generally not sufficient since better network performance can be achieved by increasing more network facilities. However, doing this eventually increases the network cost. Thus, the comparison of topologies must be performed by using an evaluation function that includes both the network performance metric and the network cost. In this paper, we propose a model to find the optimum regular logical topology for wavelength routed WDM networks. ShuffleNet, de Bruijn graph, hypercube, Manhattan Street Network, and GEMNet are the five well-known and commonly used regular topologies compared in this paper. By solving the two subproblems on node placement optimization, and routing and wavelength assignment, we obtain the evaluation function used in the topology comparison. Numerical results show that GEMNet is the optimum logical topology for the wavelength routed WDM networks, where it can take one of the three forms of ShuffleNet, de Bruijn graph, and its own configurations.

A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.

Although IP Multicast offers efficient data delivery for large group communications, the most critical issue delaying widespread deployment of IP Multicast is the scalability of multicast forwarding state as the number of multicast groups increases. Sender-Initiated Multicast (SIM) was proposed as an alternative multicast forwarding scheme for small group communications with incremental deployment capability. The key feature of SIM is in its Preset mode with the automatic SIM tunneling function, which maintaining forwarding information states only on the branching routers. To demonstrate how SIM increases scalability with respect to the number of groups, in this paper we evaluate the proposed protocol both through simulations and real experiments. As from the network operator's point of view, the bandwidth consumption, memory requirements on state-and-signaling per session in routers, and the processing overhead are considered as evaluation parameters. Finally, we investigated the strategies for incremental deployment.

This paper investigates the application of the computational model of Cellular Automata (CA) for pattern classification of real valued data. A special class of CA referred to as Fuzzy CA (FCA) is employed to design the pattern classifier. It is a natural extension of conventional CA, which operates on binary string employing boolean logic as next state function of a cell. By contrast, FCA employs fuzzy logic suitable for modeling real valued functions. A matrix algebraic formulation has been proposed for analysis and synthesis of FCA. An efficient formulation of Genetic Algorithm (GA) is reported for evolution of desired FCA to be employed as a classifier of datasets having attributes expressed as real numbers. Extensive experimental results confirm the scalability of the proposed FCA based classifier to handle large volume of datasets irrespective of the number of classes, tuples, and attributes. Excellent classification accuracy has established the FCA based pattern classifier as an efficient and cost-effective solutions for the classification problem.

We investigated the use of AlOx:N/SiNy stacked gate dielectric as an alternate gate dielectric, which were prepared by alternately repeating sub-nanometer deposition of Al2O3 from an alkylamine-stabilized AlH3 + N2O gas mixture and rapid thermal nitridation in NH3. The negative fix charges, being characteristics of almina, were as many as 3.91012 cm-2 in the effective net charge density. The effective dielectric constant and the breakdown field were 8.9 and 8 MV/cm, respectively, being almost the same as pure Al2O3. And we have demonstrated that the leakage current through the AlOx:N/SiNy stacked gate dielectric with a capacitance equivalent thickness (CET) of 1.9 nm is about two orders of magnitude less than that of thermally-grown SiO2. Also, we have confirmed the dielectric degradation similar to the stress-induced leakage current (SILC) mode and subsequent soft breakdown (SBD) reported in ultrathin SiO2 under constant current stress and a good dielectric reliability comparable to thermally-grown ultrahin SiO2. From the analysis of n+poly-Si gate metal-insulator-semiconductor field effect transistor (MISFET) performance, remote coulomb scattering due to changes in the gate dielectric plays an important role on the mobility degradation of MISFET with AlON/SiON gate stack.

This paper proposes a decentralized and asynchronous replica control method based on a fair assignment of the variation in numerical data that has weak consistency for loosely coupled database systems managed or used by different organizations of human activity. Our method eliminates the asynchronous abort of already committed transactions even if replicas in all network partitions continue to process transactions when network partitioning occurs. A decentralized and asynchronous approach is needed because it is difficult to keep a number of loosely coupled systems in working order, and replica operations performed in a centralized and synchronous way can degrade the performance of transaction processing. We eliminate the transaction abort by fairly distributing the variation in numerical data to replicas according to their demands and updating the distributed variation using only asynchronously propagated update transactions without calculating the precise global state among reachable replicas. In addition, fairly assigning the variation of data to replicas equalizes the disadvantages of processing update transactions among replicas. Fairness control for assigning the data variation is performed by averaging the variation requested by the replicas. A simulation showed that our system can achieve extremely high performance for processing update transactions and fairness among replicas.

This note considers a problem of minimum length scheduling for a set of messages subject to precedence constraints for switching and communication networks, and shows some improvements upon previous results on the problem.

Penumbral imaging is a technique which exploits the fact that spatial information can be recovered from the shadow or penumbra that an unknown source casts through a simple large circular aperture. Since the technique is based on linear deconvolution, it is sensitive to noise. In this paper, a two-step method is proposed for decoding penumbral images: first, a noise-reduction algorithm based on ICA-domain (independent component analysis-domain) shrinkage is applied to smooth the given noise; second, the conventional linear deconvolution follows. The simulation results show that the reconstructed image is dramatically improved in comparison to that without the noise-removing filters, and the proposed method is successfully applied to real experimental X-ray imaging.