Digital halftoning is a well-known technique in image processing to convert an image having several bits for brightness levels into a binary image consisting only of black and white dots. A great number of algorithms have been presented for this problem, some of which have only been evaluated just by comparison with human eyes. In this paper we formulate the digital halftoning problem as a combinatiorial problem which allows an exact solution with graph-theoretic tools. For this, we consider a d-dimensional grid of n := Nd pixels (d 1). For each pixel, we define a so-called k-neighborhood, k {0,...N - 1}, which is the set of at most (2k + 1)d pixels that can be reached from the current pixel in a distance of k. Now, in order to solve the digital halftoning problem, we are going to minimize the sum of distances of all k-neighborhoods between the original picture and the halftoned one. We show that the problem can be solved in linear time in the one-dimensional case while it looks hopeless to have a polynomial-time algorithm in higher dimension including the usual two-dimensional case. We present an exact algorithm for the one-dimensional case which runs in O(n) time if k is regarded to be a constant. For two-dimensional case we present fast approximation techniques based on space filling curves. An experimental comparison of several implementations of approximate algorithms proves that our algorithms are of practical interest.

We define the Reallocation Problem to determine whether we can move products from their current store-houses to target storehouses in a number of moves which is less than or equal to a given number. This problem is defined simply and can be applied to many practical problems. We give necessary and sufficient conditions for feasibility for Reallocation Problems under various conditions, and propose liner time algorithms, when the volume of the products is restricted to 1. Moreover, we show that the Reallocation Problem is NP-complete in the strong sense, when the volume of the products is not restricted.

The Voronoi diagram is the most fundamental and useful concept in computational geometry. To understand impacts of non-Euclidean geometry on computational geometry, this paper investigates the Voronoi diagram in hyperbolic space. We first present characterizations of this diagram by means of the Enclidean Voronoi diagram, and based on them propose efficient algorithms to construct it. Some applications are also mentioned.

This paper proposes a new formulation which minimizes the differential entropy for an optimal control problem. The conventional criterion of the optimal regulator control is a standard quadratic cost function E[M{x(t)}2} + N{v(t)}2], where x(t) is a state variable, u(t) is an input value, and M and N are positive weights. However, increasing the number of the variables of the system it is complex to find the solution of the optimal regulator control. Therefore, the simplicity of the solution is required. In contrast to the optimal regulator control, we propose the minimum entropy control which minimizes a differential entropy of the weighted sum of x(t) and u(t). This solution is derived on the assumptions that the linear control and x(t)u(t) 0 are satisfied. As the result, the formula of the minimum entropy control is very simple and clear. This result will be useful for the further work with multi variables of simple control formulation.

A calibrating analog-to digital (A/D) converter employing a T-Model neural network is described. The T-Model neural-based A/D converter architecure is presented with particular emphasis on the elimination of local minimum of the Hopfield neural network. Furthermore, a teacher forcing algorithm is presented and used to synthesize the A/D converter and correct errors of the converter due to offset and device mismatch. An experimental A/D converter using standard 5-µm CMOS discrete IC circuits demonstrates high-performance analog-to-digital conversion and calibrating.

In this paper, we give an algorithm which, given a set F of at most n-k faulty nodes, and two sets S={s1, , sk} and T = {t1,, tk}, 1kn, of non-faulty nodes in n-dimensional hypercubes Hn, finds k fault-tree node disjoint paths sitje, where (j1, , Jk) is a permutation of (1, , k), of length at most n + k in O(kn log k) time. The result of this paper implies that n disjoint paths of length at most 2n for set-to-set node disjoint path problem in Hn can be found in O(n2 log n) time.

It is well recognized that the electromagnetic interference due to indirect electrostatic discharge (ESD) is not always proportional to the ESD voltage and also that the lower voltage ESD sometimes causes the more serious failure to high-tech information equipment. In order to theoretically examine the peculiar phenomenon, we propose an analytical approach to model the indirect ESD effect. A source ESD model is given here using the spark resistance presented by Rompe and Weizel. Transient electromagnetic fields due to the ESD event are analyzed, which are compared with the experimental data carefully given by Wilson and Ma. A model experiment for indirect ESD is also conducted to confirm the validity of the ESD model presented here.

Polynomials are called permutation polynomials if they induce bijective functions. This paper investigates algebraic properties of permutation polynomials over a finite field, especially properties associated with permutation cycles. A permutation polynomial has a simple structure but good randomness properties suitable for applications. The cycle structure of permutations are considered to be related to randomness. We investigate the algebraic structure from the viewpoint of randomness. First we show the relationship between polynomials and permutations using a matrix equation. Then, we give a general form of a permutation polynomial corresponding to a product C1C2Ck of pairwise disjoint cycles. Finally, permutation polynomials with fixed points -or with 2, 3 and 4-cycles -and their compositions are given together with distribution of degree of the permutation polynomials.

We propose a parallel parsing algorithm based on Earley's method, which works in O(log2n) time using O(n4.752) processors on CREW PRAM. This algorithm runs with less number of precessors compared with previously proposed W. Rytter's algorithm.

We have developed the Epi-Base SATURN process as a silicon bipolar process technology which can be applied to optical transmission LSIs. This process technology, to which low temperature selective epitaxial growth technology is applied, is based on the SATURN process. By performing selective epitaxial growth for base formation in 2 steps, transistors with a 40GHz maximum cut-off frequency have been fabricated. In circuit simulation based on SPICE parameters of transistors, the target performance required for 2.4 Gbit/s optical interface LSIs has been achieved.

A new superresolution technique is proposed for high-resolution estimation of the scattering analysis. For complicated multipath propagation environment, it is not enough to estimate only the delay-times of the signals. Some other information should be required to identify the signal path. The proposed method can estimate the frequency characteristic of each signal in addition to its delay-time. One method called modified (Root) MUSIC algorithm is known as a technique that can treat both of the parameters (frequency characteristic and delay-time). However, the method is based on some approximations in the signal decorrelation, that sometimes make problems. Therefore, further modification should be needed to apply the method to the complicated scattering analysis. In this paper, we propose to apply a time-domain null filtering scheme to reduce some of the dominant signal components. It can be shown by a simple experiment that the new technique can enhance estimation accuracy of the frequency characteristic in the Root-MUSIC algorithm.

This paper proposes a method to predict and control noise voltage caused by electrostatic discharge (ESD) to electronic equipment. The relationship of grounding system configurations for a typical set of equipment to ESD immunity has been derived using a mechanism of ground potential variations. The equivalent circuit representing ground elements as lumped constants enables us to predict the transient ground potential differences between PCB (Printed Circuit Board) ground planes connected via signal cables and induced noise voltage at the receiving end. The calculation shows that the contribution of ground potential differences to noise voltage is comparable to that of the electromagnetic coupling between the discharge current on the enclosure and the circuit loops. The calculation also shows some characteristic results, such as; the induced noise voltage is remarkably dependent on the unbalance in ground cable lengths and on the impedance of ground conductors connecting PCBs, especially when the equipment uses a single-point grounding system. These characteristics were confirmed by measurements of induced ground potential differences, noise voltage and immunity levels. Thus the proposed method is shown to be very effective to analyze the dependency of grounding conditions on ESD immunity and to improve ESD immunity in equipment design.

This letter proposes a new shaping algorithm (CRSA: CDV Reduction Shaping Algorithm) that can freely reduce the maximum CDV value of a cell stream to any predetermined value. There is a trade off between shaping delay and the maximum CDV value reduction achieved when using CRSA. The shaper using CRSA (CR-shaper) output satisfies the Peak Cell Rate Reference Algorithm set with the CR-shaper parameters.

Six chips of the GaAs standard cell LSIs have been developed for a synchronous digital hierarchy (SDH) interface unit in 10 Gbit/s optical communication systems. Two of them are the frame termination LSIs for SDH, and four are the byte multiplexing and demultiplexing LSIs. The LSI configuration with a careful thermal design were needed to realize a natural air-cooling operation. As a result, the unit was composed of eight chips with six kind of LSIs and these LSIs consist of 1 K to 3 K gates. The LSIs were designed with the standard cell libraries based on 0.5µm gate DCFL (Direct Coupled FET Logic) operating at a low power supply voltage of 1.5V. The propagation delay time of standard DCFL inverter was 25 ps with a power consumption of 0.45mW in the experimental results. The LSI design methodology using these libraries were discussed to achieve the data processing of 1.25 Gbit/s signals under a natural air-cooling condition. The maximum operating speeds of them were at least 1.4 GHz and the power consumptions were as low as under 1.8 W, which resulted in fully high speed operations under a natural air-cooling condition at an ambient temperature of 100.

Recently, ABR has been attracting attention as a new service category of ATM, and the methodology to realize ABR is being actively discussed in the ATM Forum. ABR is expected to become a suitable class for supporting LAN services on ATM networks. To this end, a technical foundation must be established in which bandwidth is effectively utilized and quality is guaranteed. In order for ABR to use a portion of the bandwidth that is not used by high-priority classes (CBR, VBR), it is necessary to appropriately estimate the unused portion of the bandwidth. Due to the fact that the unused portion of the bandwidth in ATM networks fluctuates, such fluctuations must be taken into account. This paper describes ABR connection admission control and design of the congestion detecting point in an ABR buffer using Allan variance of the unused portion of the bandwidth.

A novel method of multichannel surface EMG processing has been developed to compensate for the distortion in bipolar surface EMG signals due to the movement of innervation zones. The distortion of bipolar surface EMG signals was mathematically described as a filtering function. A compensating technique for such distorted bipolar surface EMG signals was developed for the brachial biceps during dynamic contractions in which the muscle length and tension change. The technique is based on multichannel surface EMG measurement, a method for estimating the movement of an innervation zone, and the inverse filtering technique. As a result, the distorted EMG signals were compensated and transformed into nearly identical waveforms, independent of the movement of the innervation zone.

The charge neutralized at a small gap discharge has been evaluated from measured electromagnetic fields by two methods. The small gap discharges simulate ESD events. The evaluated charge decreases rapidly as a step shape immediately in a moment of the discharge. The accumulated static charge and the risetime of the neutralization step increase with the gap length. When the gap length is 0.1mm, risetime and the initial static charge are about 0.3ns and 5.6nC, respectively.

The base transit time of an Aluminum-graded-base PNp AlGaAs/GaAs heterojunction bipolar transistor (HBT) was studied in order to clarify the effect of aluminum grading in the base. Theoretical analysis using a classical drift diffusion model with velocity saturation at the base-collector junction and a high base quasielectric field (58 keV/cm) created by 20%-aluminum linear grading in a 400 base, leads to a base transit time (τb) of 0.9 ps. The base transit time is reduced by four times, compared to the base transit time of 3.6 ps without aluminum grading in the base. In order to demonstrate this advantage, we fabricated aluminum-graded-base PNp AlGaAs/GaAs heterojunction transistor which employs a 20%-aluminum linear graded 400 -wide base. The device with a 2 µm 10 µm emitter showed high RF performance with a cut-off frequency (ft) of 37 GHz and a maximum oscillation frequency (fmax) of 30 GHz at a collector current density of 3.4 104 A/cm2. Further analysis using direct parameter extraction of a small signal circuit model under the collector current density of 1.1-9.9104 A/cm2 indicated the intrinsic transit time, which is the sum of the base transit time and the collector depletion layer transit time (τSC), was as low as 2.3 ps under lowinjection level. Subtracting the collector depletion-layer transit time from the intrinsic time leads to a base transit time of 1.1 ps, which is close to the theoretical base transit time and is the shortest value ever reported. The structure is very attractive for pnp-type AlGaAs HBTs combined with Npn HBTs for complementary applications.

Using fundamental device and circuits, we have realized three functions required for synaptic connections in self-organizing neural networks: long term memory of synaptic weights, fixed total amount of synaptic weights in a neuron, and lateral inhibition. The first two functions have been condensed into an optical adaptive device and circuits with floating gates. Lateral inhibition has been realized by a winner-take-all circuit and a following lateral excitatory connection circuit. We have fabricated these devices and circuits using CMOS technology and confirmed the three functions. In addition, topological mapping, which is essential for feature extraction, has been formed in a primitive network constructed with the fundamental device and circuits.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.