In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (Dit) on the order of 1011eV-1cm-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

We investigated the low temperature formation of Pd2Si on Si(100) with TiN encapsulating layer formed at 500°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x1015 cm-2 for B+. The uniform Pd2Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500°C. The estimated Schottky barrier height to hole of 0.20 eV (qφBp) was realized for n-Si(100).

Copper (Cu) electroless plating was conducted on planar and microstructured polydimethylsiloxane (PDMS) substrates. In this study, organic thin films terminated with nitrogen (N)-containing groups, e.g. poly (dimethylaminoethyl methacrylate) brush (PDMAEMA), aminopropyl trimethoxysilane monolayer (APTES), and polydopamine (PDA) were used to anchor palladium (Pd) catalyst. While electroless plating was successfully promoted on all sample surfaces, PDMAEMA was found to achieve the best adhesion strength to the PDMS surfaces, compared to APTES- and PDA-covered PDMS substrates, due to covalent bonding, anchoring effects of polymer chains as well as high affinity of N atoms to Pd species. Our process was also successfully applied to the electroless plating of microstructured PDMS substrates.

A novel activation method for a B dopant implanted in a Si substrate using a soft X-ray undulator was examined. As the photon energy of the irradiated soft X-ray approached the energy of the core level of Si 2p, the activation ratio increased. The effect of soft X-ray irradiation on B activation was remarkable at temperatures lower than 400°C. The activation energy of B activation by soft X-ray irradiation (0.06 eV) was lower than that of B activation by furnace annealing (0.18 eV). The activation of the B dopant by soft X-ray irradiation occurs at low temperature, although the activation ratio shows small values of 6.2×10-3 at 110°C. The activation by soft X-ray is caused not only by thermal effects, but also electron excitation and atomic movement.

As MOS transistors are scaled down, the impact of randomly placed discrete charge (impurity atoms, traps and surface states) on device characteristics rapidly increases. Significant variability caused by random dopant fluctuation (RDF) is a direct result of this, which urges the adoption of new device architectures (ultra-thin body SOI FETs and FinFETs) which do not use impurity for body doping. Variability caused by traps and surface states, such as random telegraph noise (RTN), though less significant than RDF today, will soon be a major problem. The increased complexity of such residual-charge-induced variability due to non-Gaussian and time-dependent behavior will necessitate new approaches for variation-aware design.

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550 nm. The three different modulation lengths (ML) of 500, 1000, and 2000 µm while keeping the overall MZI length constant at 1.5 cm were set as a general design rule for these 10 µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50 mA current (Is) to achieve a π phase shift, the modulation efficiency of the device was measured to be η = π /(Is· L) 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5 µsec and the 3 dB roll-off frequency (f3 dB) measured was in the excess of 400 kHz.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate Vt fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.

We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO2 interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO2 interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.

This paper describes an effective model which reproduces the dependence on the source/drain (S/D) process of the reverse short channel effect (RSCE) of the MOSFET threshold voltage (Vth). It is useful for local modeling which is effective within the limited process conditions. The proposed model is based on the physics where the key factor of RSCE is the dopant pile-up in the Si/SiO2 interface. The purpose of the model is for TCAD to be put to actual use as a quick solution tool. The calculation cost is much lower than a pair diffusion model, because the model is implemented in a conventional process simulator that solves one equation for each impurity. The capability of the simplified model is investigated for the dependence of various process conditions on the RSCE. Using our model, we also report the application of both the actual n-channel and p-channel MOSFETs.

Ultra shallow low-resistive junction formation has been investigated for sub-100-nm MOSFETs using antimony implantation. The pileup at the Si/SiO2 interface and the resulting dopant loss during annealing is a common obstacle for antimony and arsenic to reduce junction sheet resistance. Though implanted arsenic gives rise to pileup even with a few seconds duration RTA (Rapid Thermal Annealing), antimony pileup was suppressed with the RTA at relatively low temperature, such as 800 or 900. As a result, low sheet resistance of 260 Ω/sq. was obtained for a 24 nm depth junction with antimony. These results indicate that antimony is superior to arsenic as a dopant for ultra shallow extension formation. However, increase in antimony concentration above 11020 cm-3 gives rise to precipitation and it limits the sheet resistance reduction of the antimony doped junctions. Redistribution behaviors of antimony relating to the pileup and the precipitation are discussed utilizing SIMS (Secondary Ion Mass Spectrometry) depth profiles.

Internet access via mobile communications networks is growing rapidly; NTT DoCoMo's Internet access service using cellular phones, known as i-mode and started in February 1999, is no exception. The i-mode service enables the user to send e-mail and access Web sites for a variety of information through simple operation of a mobile terminal equipped with a browser. As a result, the traffic to be carried by the PDC (Personal Digital Cellular)-- Packet mobile communication network, which is used to provide the i-mode service, is also increasing rapidly. To meet this growing demand, the switching systems in place are being either increased in capacity or replaced by more powerful ones. To plan this effectively, it is necessary to make an accurate evaluation of the i-mode processing capacity. We have developed a new method of evaluating processing capacity, which is based on the conventional method but takes account of the characteristics specific to the PDC-Packet network. This paper discusses the method of evaluating the processing capacity of switching systems used in the PDC-Packet mobile network.

We propose an effective model that can reproduce the reverse short channel effect (RSCE) of the threshold voltage (Vth) of MOSFETs using a conventional process simulator that solves one equation for each impurity. The proposed model is developed for local modeling which is effective within the limited process conditions. The proposed model involves the physics in which RSCE is due to the pile up of channel dopant at the Si/SiO2 interface. We also report the application to actual device design using our model. The calculation cost is much lower than for a pair diffusion model, and device design in an acceptable turn around time is possible.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

We have systematically studied the characteristics of Si doping in GaAs grown on (311)A GaAs substrates by molecular beam epitaxy. The growth temperature dependence of Si doping has been investigated. It is found that the conduction-type sharply changes from p-type to n-type with decreasing growth temperature at a critical temperature of 430-480. The highest hole density obtained for uniformly doped layers was 1.51020 cm-3, while for δ-doped layers the sheet hole density as high as 2.61013 cm-2 was achieved. This is the highest hole density ever reported for δ-doped GaAs.