Fully embedded spiral inductors in a low loss dielectric multi-layer were designed and fabricated using a low temperature co-fired ceramics (LTCC) technology for RF SIP (system in package) integrations. The line width/space and the number of spiral layers were optimized within five layers of LTCC dielectric for high Q-factor, high self-resonant frequency (SRF), process easiness, and compact size. The embedded multi-layer spiral inductors reveal better performance in terms of Q-factor, SRF and the effective inductance Leff than planar spiral inductors of the same dimension and number of turns. The optimized multi-layer spiral inductor shows maximum Q of 56, Leff of 6.6 nH at Qmax and SRF of 3.6 GHz while planar spiral inductors have maximum Q of 49, Leff of 5.8 nH at Qmax and SRF of 3.0 GHz.

In this paper, we propose a packet-scheduling algorithm, called the Class-level Service Lagging (CSL) algorithm, that guarantees multiple delay bounds for multi-class traffic in packet networks. We derive the associated schedulability test conditions, which are used to determine call admission. We first introduce a novel implementation of priority control, which has a conventional and simple form. We show how the efforts to confirm the logical validity of that implementation are managed to reach the definition of the CSL algorithm. The priority control is realized by imposing class-level unfairness in service provisioning, while the underlying service mechanism is carried out using the notion of fair queueing. The adoption of fair queueing allows the capability to maintain the service quality of the well-behaving traffic even in the presence of misbehaving traffic. We call this the firewall property. Simulation results demonstrate the superiority of the CSL algorithm in both priority control and firewall functionality. We also describe how the CSL algorithm is implementable with a computational complexity of O(1). Those features as well as the enhanced scalability, which results from the class-level approach, confirm the adequacy of the CSL algorithm for the fast packet networks.

This letter presents a code which corrects single bit errors in any location of the word as well as l-bit burst errors occurred in an important part of the word. The proposed code is designed by product of the parity check matrix of the l-bit burst error correcting codes and the matrix which converts input unequal errors into equal errors. This letter also demonstrates the evaluation of the code, and presents the extended codes with two-level burst error correcting capabilities by interleaving.

We present a novel kind of integrate-and-fire circuit (IFC) with two periodic inputs: a pulse-train stimulation input and a base input. We clarify that the system state is quantized by the pulse-train stimulation input. Then the system dynamics is described by a return map with quantized state (Qmap). By changing the shape of the base input, various Qmaps can be obtained. The Qmap exhibits co-existence state of various super-stable periodic orbits, and the IFC outputs one of corresponding super-stable periodic pulse-trains depending on the initial state. For a typical case, we clarify the number of co-existing periodic pulse-trains theoretically for the stimulation frequencies. Constructing a simple test circuit, typical phenomena can be verified in the laboratory.

This paper studies an integrate-and-fire circuit with a periodic input. It has two states and has rich dynamics: as a DC input varies, it can exhibit period doubling bifurcation to chaos; as a periodic input is applied, the periodic or chaotic phenomenon (for a DC input) is changed into interesting synchronous or asynchronous phenomenon. Using a mapping procedure, we can elucidate parameter subspace in which the synchronous phenomena occur. Using a test circuit, typical phenomena can be verified in the laboratory.

An electrophysiological experiment showed that spike timing was precise to less than one millisecond. This result indicates the possibility in the precise time codings. For a high accurate time coding, reconsideration of a neural mechanism which decides firing time is required. From such viewpoint, we quantitatively examined change in firing time with interference between two synaptic inputs through Hodgkin-Huxley (HH) and integrate-and-fire (IF) model neurons. The precise firing times in the HH model neuron were extremely different from those in the IF model neuron. In this paper, the relations of input intensity to firing time are investigated in the other more two pulse generation models: Morris-Lecar (ML) and FitzHugh-Nagumo (FN) model. The result of the ML model in a certain parameter set (type-I) exhibited monotone decreasing like that of the IF model while the result of the ML model in the otter parameter set (type-II) exhibited non-monotone decreasing like that of the HH model. The result of the FN model exhibited non-monotone decreasing like the HH model despite its qualitativeness. Next the firing patterns in the four model neurons on a model of V1 (primary visual area) and LGN (lateral geniculate nucleus) with circular and mutual excitatory connections are investigated to show how dependent on model neurons the firing patterns are. The spikes in the HH, the ML type-II, and the FN model neurons elicited synchronous oscillations while the spikes in the IF and the ML type-I model neurons did not; the firing patterns dramatically changed with the dependence on the model neurons.

This paper studies mutually coupled integrate-and-fire type chaotic oscillators. The coupling is realized by impulsive switchings and the system exhibits various synchronous and asynchronous phenomena. We give a basic classification of the chaos synchronization phenomena and their breakdown patterns. The stability of the synchronous states can be confirmed using the piecewise exact solutions, and the basic mechanism of the phenomena can be elucidated by a simple geometric consideration. The typical phenomena are confirmed in the laboratory.

In this paper, we consider the Integrate-and-Fire Model (ab. IFM) with two periodic inputs. The IFM outputs a pulse-train which is governed by a one dimensional return map. Using the return map, the relationship between the inputs and the output is clarified: the first input determines the global shape of the return map and the IFM outputs various periodic and chaotic pulse-trains; the second input quantizes the state of the return map and the IFM outputs various periodic pulse-trains. Using a computer aided analysis method, the quantized return map can be analyzed rigorously. Also, some typical phenomena are confirmed in the laboratory.

Backfire quadrifilar helical antennas combined with parasitic loops are investigated in detail, focusing on clarifying the function of parasitic loops. First, the basic property is examined for the case of one parasitic loop, and it is found that the loop behaves as a director when the circumferential length of the loop is nearly 0. 9λ, and a reflector when the circumferential length of the loop is nearly 1. 2λ provided the distance between the parasitic loop and the top plane of helical antennas is approximately 0. 1λ, where λ is the wavelength. Next, the function of the parasitic loop is investigated by comparing the current distributions on the helices and the loop with those on a monofilar helix with a ground plane. It is found that the function of the parasitic loop is quite different from that of the ground plane. Then, the case of two parasitic loops is examined, and it is shown that the use of two parasitic loops is very effective and simple measures to control the radiation pattern and gain of the backfire quadrifilar helical antennas. Finally, for this type of antennas with two parasitic loops, an example of structural parameters suited to the use in satellite communications is presented.

This paper proposes a protocol to support mobile hosts in IPv6 by introducing a new addressing architecture and a new hop-by-hop option. This protocol also allows a mobile host to communicate with another host via a firewall machine which drops packets from untrustworthy hosts. The new addressing scheme is based on the separation of the identifier and the location of a mobile host. This is a straightforward implementation of the basic concept of VIP, a protocol providing seamless mobility in IPv4. The new hop-by-hop option of IPv6 allows a firewall machine to authenticate the source host of the forwarded packet with negligible overhead. The author plans to implement this protocol on several operating systems in the near future.

A new GaAs negative voltage generator suitable for biasing a GaAs MESFET power amplifier has been successfully developed and applied to a 1.9-GHz single-chip transmit/receive (T/R)-MMIC front-end including a power amplifier, a T/R-switch, and so on. To meet various requirements necessary for integration with a power amplifier, four new circuit techniques are introduced into this generator: (1)complementary charge pump operation to suppress spurious outputs. (2)an SCFL-to-DCFL cross-coupled level shifter to ensure a wide operation voltage range, (3)a level control circuit to reduce output voltage deviation caused by output current, and (4)interface and layout designs to achieve sufficient isolation between the power amplifier and the generator. The generator was incorporated into the MMIC front-end, and it was tested with a 30-lead shrink small outline package. With 20-to-500-MHz external input signals of more than -15 dBm, the generator produces negative voltages from -1.0 to -2.6 V for a wide range of suppiy voltages from 1.6 to 4.5 V. The current consumption is as low as 3.2 mA at 3 V. When a 22-dBm output is delivered through the power amplifier biased by the generator, low spurious outputs below -70 dBc are achieved. and gate-bias voltage deviations are suppressed to within 0.06 V even when a gate current of -140 µA flows through the amplifier. The generator also enables high speed operation of charge time below 200 ns, which is effective in TDMA systems such as digital cordless telephone systems. In layout design, electromagnetic simulation was utilized for estimating sufficient isolation between circuits in the MMIC. This negative voltage generator and its application techniques will enable GaAs high-density integration devices as well as single voltage operation of a GaAs MESFET power amplifier.