It is crucial to make Si wafer surfaces ultraclean in order to realize such advanced processes as the low-temperature process and the high-selectivity in the ULSI production. The ultra clean wafer surface must be perfectly free from particles, organic materials, metallic impurities, native oxide, surface microroughness, and adsorbed molecule impurities. Since the metallic contamination on the wafer surface, which is one of the major contaminants to be overcome in order to come up with the ultra clean wafer surface, has the fatal effect on the device characteristics, the metallic impurities in the wafer surface must be suppressed at least below 1010 atoms/cm2. Meanwhile the current dry processes such as reactive ion etching or ion implantation, suffer the metallic contamination of 10121013 atoms/cm2. The wet process becomes increasingly important to remove the metallic impurities introduced in the dry process. Employing a new evaluation method, the metallic impurity segregations at the inrerface between the Si and liquid employed in the wet cleaning process of the Si surface such as ultrapure water and various clemicals were studied. This article clearly indicate that it is important to suppress the metallic impurities, such as Cu, which can exchange electrons with Si to be segregated, at least below the 10 ppt level in ultrapure water and liquid chemical such as HF, H2O2, which are employed in the final step of the wet cleaning. When the ultrapure water rinsing is performed in the ambience containing oxygen, the native oxide grows accompanying an inclusion of metals featuring lower electron negativity than Si. It is revealed that, in order to provent the metallic impurity precipitation, it is require not only to remove metallic impurities from ultrapure water but also to keep the cleaning ambience without oxygen, such as the nitrogen ambience, so as to suppress the native oxide formation.

This letter discusses the quality improvement of reconstructed images in diffraction tomography. An efficient iterative procedure based on the modified Newton-Kantorovich method and the Gerchberg-Papoulis algorithm is presented. The simulated results demonstrate the property of high-quality reconstruction even for cases where the first-order Born approximation fails.

This paper designs and evaluates highly parallel VLSI processors for real time 2-D state-space digital filters using hierarchical behavioral description language and synthesizer. The architecture of the 2-D state-space digital filtering system is a linear systolic array of homogeneous VLSI processors, each of which consists of eight processing elements (PEs) executing 1-D state-space digital filtering with multi-input and multi-output. Hierarchical behavioral description language and synthesizer are adopted to design and evaluate PE's and the VLSI processors. One 16 bit fixed-point PE executing a (4, 4)-th order 2-D state-space digital filtering is described on the basis of distributed arithmetic in about 1,200 steps by the description language and is composed of 15 K gates in terms of 2 input NAND gate. One VLSI processor which is a cascade connection of eight PEs is composed of 129 K gates and can be integrated into one 1515 [mm2] VLSI chip using 1 µm CMOS standard cell. The 2-D state-space digital filtering system composed of 128 VLSI processors at 25 MHz clock can execute a 1,0241,024 image in 1.47 [msec] and thus can be applied to real-time conventional video signal processing.

This paper discusses a computer-aided network planning support system called PIGEON that has been developed primarily for advancing countries implementing the applicability to various types of networks and the supportability to the sensitivity analysis. For the implementation of the applicability, the customization by reflecting existing network facilities and their accompanying restrictive conditions into a design result is focused. A case study on the customization shows the effectiveness of the reflection. The procedures are given of the sensitivity analysis in order to examine and to evaluate the effect of the uncertain factors in network planning. In particular, a method called "network modification" is proposed for the sensitivity analysis for uncertain factors associated with a partial network. The network modification efficiently integrates network planner's judgments into a design result by the interactive method. In addition, this paper describes the importance of streamlining the data input and the evaluation of design results, showing the operating time required for each work phase in network planning.

The elementary formal system (EFS, for short) is a kind of logic program which directly manipulates character strings. This paper outlines in brief the authors' studies on algorithmic learning theory developed in the framework of EFS's. We define two important classes of EFS's and a new hierarchy of various language classes. Then we discuss EFS's as logic programs. We show that EFS's form a good framework for inductive inference of languages by presenting model inference system for EFS's in Shapiro's sense. Using the framework we also show that inductive inference from positive data and PAC-learning are both much more powerful than they have been believed. We illustrate an application of our theoretical results to Molecular Biology.

Lexical-Functional Grammars (LFG's) were introduced to define the syntax of natural languages. In LFG's, each node of a derivation tree has some attributes. An LFG G consists of a context-free grammar (cfg) G0 called the underlying cfg of G and a description Pfs of constraints between the values of the attributes. Pfs can specify (1) constraints between the value of an attribute of a node and those of its children, and (2) constraints between the value of an attribute of a node called a controller and that of a node called its controllee. RLFG's were introduced as a subclass of LFG's. In RLFG's, only constraints between the value of an attribute of a node and those of its children can be specified. It is shown in this paper that the class of languages generated by RLFG's is equal to the class of recursively enumerable languages. Some restrictions on LFG's were proposed for the purpose of efficient parsing. Among them are (1) the condition called a valid derivation, and (2) the condition that the underlying cfg is cycle-free. For an RLFG G, if the production rules of the underlying cfg of G are of the form AaB or Aa for nonterminal symbols A, B and a terminal symbol a, then G is called an R-RLFG. Every R-RLFG satisfies the above restriction (1) and (2). It is also shown in this paper that the class of languages generated by R-RLFG's contains an NP-hard language, which means that parsing in deterministic polynomial time of LFG's is impossible in general (unless PNP) even if the above restrictions (1) and (2) are satisfied.

In this paper, we consider the polynomial time inferability from positive data for unions of two tree pattern languages. A tree pattern is a structured pattern known as a term in logic programming, and a tree pattern language is the set of all ground instances of a tree pattern. We present a polynomial time algorithm to find a minimal union of two tree pattern languages containing given examples. Our algorithm can be considered as a natural extension of Plotkin's least generalization algorithm, which finds a minimal single tree pattern language. By using this algorithm, we can realize a consistent and conservative polynomial time inference machine that identifies unions of two tree pattern languages from positive data in the limit.

The introduction of Integrated Services Digital Networks (ISDNs) poses a variety of new questions on telecommunications network design and planning. Furthermore, the formulation of traditional network design and planning problems need to be revisited in the ISDN context. This paper presents an overview of the recent progress and new challenges in developing ISDN design and planning methodologies that exploit revolutionary new telecommunications technologies. It will cover some important issues for ISDN design and planning, and will concentrate on three issues that are of particular importance: Design of networks with digital information transfer capabilities, design of networks with advanced network/traffic control techniques, and use of reliability objectives for network design and planning.

This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.

Over the past few years, the drive towards optimization and globalization of business activities has mandated the integration of various services, an increase in system scale, and the networking of a variety of systems. These requirements can only be satisfied by the introduction of systems that are able to accommodate and control multiple media and integrate LANs and PBXs synergistically. This paper proposes an architecture for next generation private networks called ANS (Areal Networking System) that is targeted at achieving flexible customization in an effort to meet a wide variety of user requirements as well as the ability to efficiently handle multimedia services. Based upon the clarification of various requirements on the ANS architecture, this paper defines two models for the ANS architecture. These models introduce modular building blocks in hierarchical structures that facilitate the custom design of networks. The key technologies for the ANS architecture are also discussed; for example, schemes for logically networking control functions by using virtual connections and a way to implement the LAN function.

One of the problems with subband image coding is the increase in image sizes caused by filtering. To solve this, it has been proposed to process the filtering by transforming input sequence into a periodic one. Then filtering is implemented by circular convolution. Although this technique solves the problem, there are very strong restrictions, i.e., limitation on the filter type and on the filter bank structure. In this paper, development of this technique is presented. Consequently, any type of linear phase FIR filter and any structure of filter bank can be used.

In this paper, we deal with inductive inference of an indexed family of recursive languages. We give two sufficient conditions for inductive inferability of an indexed family from positive data, each of which does not depend on the indexing of the family. We introduce two notions of finite cross property for a class of languages and a pair of finite tell-tales for a language. The former is a generalization of finite elasticity due to Wright and the latter consists of two finite sets of strings one of which is a finite tell-tale introduced by Angluin. The main theorem in this paper is that if any language of a class has a pair of finite tell-tales, then the class is inferable from positive data. Also, it is shown that any language of a class with finite cross property has a pair of finite tell-tales. Hence a class with finite cross property is inferable from positive data. Further-more, it is proved that a language has a finite tell-tale if and only if there does not exist any infinite cross sequence of languages contained in the language.

Based on the Fornasini-Marchesini second local state-space (LSS) model, the coefficient sensitivities of two-dimensional (2-D) digital filters are analyzed in conjunction with frequency weighting functions. The overall sensitivity called the frequency-weighting sensitivity is then evaluated using the 2-D generalized Gramians that are newly introduced for the Fornasini-Marchesini second LSS model. Next, the 2-D filter structures that minimize the frequency-weighting sensitivity are synthesized for two cases of no constraint and scaling constraints on the state variables. Finally, an example is given to illustrate the utility of the proposed technique.

The single fault model is invalid in many cases. However, it is very difficult to generate tests for all multiple faults since an m-line circuit may have 3m --1 multiple faults. In this paper, we describe a method for generating tests for combinational circuits with multiple stuck-at faults. An input vector is a test for a fault on a target line, if it find the target line to be fault-free in the presence of undetected or undetectable lines. The test is called a robust test for fault on a target line. It is shown that the sensitizing input-pair for a completely single sensitized path can be a robust test-pair. The method described here consists of two procedures. We label these as SINGLE_SEN" procedure and DECISION" procedure. SINGLE_SEN generates a single sensitized path including a target line on it by using a PODEM-like method which uses a new seven-valued calculus. DECISION determines by utilizing the method proposed by H. Cox and J. Rajski whether the single sensitizing input-pair generated by the SINGLE_SEN is a robust test-pair. By using these two procedures the described method generates robust test-pairs for the combinational circuit with multiple stuck-at faults. Finally, we demonstrate by experimental results on the ISCAS85 benchmark circuits that SINGLE_SEN is effective for an algorithmic multiple fault test generation for circuits not including many XOR gates.

Spoken language systems such as speech-to-speech dialog translation systems have been gaining more attention in recent years. These systems require full integration of speech recognition and natural language understanding. This paper presents an efficient parsing algorithm that integrates the search problems of speech processing and language processing. The parsing algorithm we propose here is regarded as an extension of the finite-state-network directed, one-pass search algorithm to one directed by a context-free grammar with retention of the time-synchronous procedure. The extended search algorithm is used to find approximately globally optimal sentence hypotheses; it does not have overhead which exists in, for example, hierarchical systems based on the lattice parsing approach. The computational complexity of this search algorithm is proportional to the length of the input speech. As the search process in the speech recognition can directly take account of the predictive information in the sentence parsing, this framework can be extended to sopken language systems which deal with dynamically varying constraints in dialogue situations.

The meaning of analogical reasoning in locally stratified logic programs are described by generalized stable model (GSM) semantics. Although studies on the theoretical aspects of analogical reasoning have recently been on the increase, there have been few attempts to give declarative semantics for analogical reasoning. This paper takes notice of the fact that GSM semantics gives meaning to the effect that the negated predicates represent exceptional cases. We define predicates that denote unusual cases regarding analogical reasoning; for example, ab(x)p(x)g(x), where p(s), q(s), p(t) are given. We also add rules with negated occurrences of such predicates into the original program. In this way, analogical models for original programs are given in the form of GSMs of extended programs. A proof procedure for this semantics is presented. The main objective of this paper is not to construct a practical analogical reasoning system, but rather to present a framework for analyzing characteristics of analogical reasoning.

Logarithmic number systems (LNS) provide a very fast computational method. Their exceptional speed has been demonstrated in signal processing and then in computer graphics. But the precision problem of LNS in computer graphics has not been fully examined. In this paper analysis is made for the problem of LNS in picture generation, in particular for circle drawing. Theoretical error analysis is made for the circle drawing. That is, some expressions are developed for the relative error variances. Then they are examined by simulation experiments. Some comparisons are also done with floating point arithmetic with equivalent word length and dynamic range. The results show that the theory and the experiments agree reasonably well and that the logarithmic arithmetic is superior to or at least comparable to the corresponding floating point arithmetic with equivalent word length and dynamic range. Those results are also verified by visual inspections of actually drawn circles. It also shows that the conversion error (from integer to LNS), which is inherent in computer graphics with LNS, does not make too much influence on the total computational error for circle drawing. But it shows that the square-rooting makes the larger influence.

This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.

An intermediate-frequency-combining (IF-combining) polarization diversity using frequency conversion is proposed. The proposed diversity requires no phase controller as opposed to the conventional IF-combining diversity. It has been theoretically clarified that this diversity has polarization insensitive bit-error-rate (BER) characteristics. The effectiveness has been confirmed by experiments in which the sensitivity dependence on the polarization is suppressed to within 0.8dB and a stable 101km fiber transmission at 600Mbit/s is achieved.

In this letter, introducing a highly accurate model for a real current mode DC-DC converter, an innovative design strategy is proposed in order to optimize circuit behavior in cases in which chaotic effects are present.