Plasmaless etching using ClF3 gas has been investigated on nitride films with different composition. For the sputter deposited and thermally grown silicon nitride films containing no hydrogen, the etch rate increases and the activation energy decreases with increase of the composition ratio of silicon to nitrogen between 0.75 and 1.3. This fact indicates that the etching is likely to proceed through the reaction between Si and ClF3. The native oxide on the silicon-nitride films can also be removed with ClF3 gas. Ultra-violet light irradiation from a low pressure mercury lamp remarkably accelerates the removal of the native oxide and the etch rate of the thermally grown silicon-nitride films. For the plasma deposited films, the etch rate is strongly accelerate with increasing hydrogen content in the films, but the activation energy hardly depends on the bounded hydrogen in the films, consistent with the results for Si etching.

This paper proposes an efficient design method of three-dimensional (3-D) recursive digital filters for video signal processing via decomposition of magnitude specifications. A given magnitude specification of a 3-D digital filter is decomposed into specifications of 1-D digital filters with three different (horizontal, vertical, and temporal) directions. This decomposition can reduce design problems of 3-D digital filters to design problems of 1-D digital filters, which can be designed with ease by conventional methods. Consequently, design of 3-D digital filters can be efficiently performed without complicated tests for stability and large amount of computations. In order to process video signal in real time, the 1-D digital filters with temporal direction must be causal, which is not the case in horizontal and vertical directions. Since the proposed method can approximate negative magnitude specifications obtained by the decomposition with causal 1-D R filters, the 1-D digital filters with temporal direction can be causal. Therefore the 3-D digital filters designed by the proposed method is suitable for real time video signal processing. The designed 3-D digital filters have a parallel separable structure having high parallelism, regularity and modularity, and thus is suitable for high-speed VLSI implementation.

Based on the Fornasini-Marchesini second model, an efficient algorithm is developed to derive the characteristic polynomial and the inverse of the system matrix from the state-space parameters. As a result, the external description of the Fornasini-Marchesini second model is clarified. A technique for designing 2-D recursive digital filters in the frequency domain is then presented by using the Fornasini-Marchesini second model. The resulting filter approximates both magnitude and group delay specifications and its stability is always guaranteed. Finally, three design examples are given to illustrate the utility of the proposed technique.

In this paper, we consider the polynomial time inferability from positive data for unions of two tree pattern languages. A tree pattern is a structured pattern known as a term in logic programming, and a tree pattern language is the set of all ground instances of a tree pattern. We present a polynomial time algorithm to find a minimal union of two tree pattern languages containing given examples. Our algorithm can be considered as a natural extension of Plotkin's least generalization algorithm, which finds a minimal single tree pattern language. By using this algorithm, we can realize a consistent and conservative polynomial time inference machine that identifies unions of two tree pattern languages from positive data in the limit.

This paper describes a super high definition (SHD) image processing system we have developed. The computing engine of this system is a parallel processing system with 128 processing elements called NOVI- HiPIPE. A new pipelined vector processor is introduced as a backend processor of each processing element in order to meet the great computing power required by SHD image processing. This pipelined vector processor can achieve 120 MFLOPS. The 128 pipelined vector processors installed in NOVI- HiPIPE yield a total system peak performance of 15 GFLOPS. The SHD image processing system consists of an SHD image scanner, and SHD image storage node, a full color printer, a film recorder, NOVI- HiPIPE, and a Super Frame Memory. The Super Frame Memory can display a ful color moving image sequence at a rate of 60 fps on a CRT monitor at a resolution of 2048 by 2048 pixels. Workstations, interconnected through an Ethernet, are used to control these units, and SHD image data can be easily transfered among the units. NOVI- HiPIPE has a frame memory which can display SHD still images on a color monitor, therefore, one processed frame can be directly displayed. We are developing SHD image processing algorithms and parallel processing methodologies using this system.

One of the problems with subband image coding is the increase in image sizes caused by filtering. To solve this, it has been proposed to process the filtering by transforming input sequence into a periodic one. Then filtering is implemented by circular convolution. Although this technique solves the problem, there are very strong restrictions, i.e., limitation on the filter type and on the filter bank structure. In this paper, development of this technique is presented. Consequently, any type of linear phase FIR filter and any structure of filter bank can be used.

Spoken language systems such as speech-to-speech dialog translation systems have been gaining more attention in recent years. These systems require full integration of speech recognition and natural language understanding. This paper presents an efficient parsing algorithm that integrates the search problems of speech processing and language processing. The parsing algorithm we propose here is regarded as an extension of the finite-state-network directed, one-pass search algorithm to one directed by a context-free grammar with retention of the time-synchronous procedure. The extended search algorithm is used to find approximately globally optimal sentence hypotheses; it does not have overhead which exists in, for example, hierarchical systems based on the lattice parsing approach. The computational complexity of this search algorithm is proportional to the length of the input speech. As the search process in the speech recognition can directly take account of the predictive information in the sentence parsing, this framework can be extended to sopken language systems which deal with dynamically varying constraints in dialogue situations.

The single fault model is invalid in many cases. However, it is very difficult to generate tests for all multiple faults since an m-line circuit may have 3m --1 multiple faults. In this paper, we describe a method for generating tests for combinational circuits with multiple stuck-at faults. An input vector is a test for a fault on a target line, if it find the target line to be fault-free in the presence of undetected or undetectable lines. The test is called a robust test for fault on a target line. It is shown that the sensitizing input-pair for a completely single sensitized path can be a robust test-pair. The method described here consists of two procedures. We label these as SINGLE_SEN" procedure and DECISION" procedure. SINGLE_SEN generates a single sensitized path including a target line on it by using a PODEM-like method which uses a new seven-valued calculus. DECISION determines by utilizing the method proposed by H. Cox and J. Rajski whether the single sensitizing input-pair generated by the SINGLE_SEN is a robust test-pair. By using these two procedures the described method generates robust test-pairs for the combinational circuit with multiple stuck-at faults. Finally, we demonstrate by experimental results on the ISCAS85 benchmark circuits that SINGLE_SEN is effective for an algorithmic multiple fault test generation for circuits not including many XOR gates.

Based on the Fornasini-Marchesini second local state-space (LSS) model, the coefficient sensitivities of two-dimensional (2-D) digital filters are analyzed in conjunction with frequency weighting functions. The overall sensitivity called the frequency-weighting sensitivity is then evaluated using the 2-D generalized Gramians that are newly introduced for the Fornasini-Marchesini second LSS model. Next, the 2-D filter structures that minimize the frequency-weighting sensitivity are synthesized for two cases of no constraint and scaling constraints on the state variables. Finally, an example is given to illustrate the utility of the proposed technique.

We have developed an advanced tool for dimensioning circuit-switched networks, called CNEP (Circuit-Switched Network Evaluation Program) , for effective design of digital networks. CNEP features a high-reliability network structure (node dispersion, double homing, etc) , both-way circuit operation, and circuit modularity (or big module size), all of which are critical for digital networks. CNEP also solves other dimensioning problems such as the cost difference between existing and newly installed circuits, and handles multi-hour traffic conditions, dynamic routing, and multiple-switching-unit nodes. Operations Research techniques are applied to produce exact and heuristic algorithms for these problems. Algorithms with good time-performance trade-off characteristics are chosen for CNEP.

A new cleaning solution (FPM; HF-H2O2-H2O) was investigated in order to remove effectively metallic impurities on the silicon wafer surface. The removability of metallic impurities on the wafer surface and the concentrations of metallic impurities adsorbed on the wafer surface from each contaminated cleaning solution were compared between FPM and conventional cleaning solutions, such as HPM (HCl-H2O2-H2O), SPM (H2SO4-H2O2), DHF (HF-H2O) and APM (NH4OH-H2O2-H2O). This new cleaning solution had higher removability of metallic impurities than conventional ones. Adsorption of some kinds of metallic impurities onto the wafer surface was a serious problem for conventional cleaning solutions. This problem was solved by the use of FPM. FPM was important not only as a cleaning solution for metallic impurities, but also as an etchant. Furthemore, this new cleaning solution made possible to construct a simple cleaning system, because the concentrations of HF and H2O2 are good to be less than 1% for each, and it can be used at room temperature.

The elementary formal system (EFS, for short) is a kind of logic program which directly manipulates character strings. This paper outlines in brief the authors' studies on algorithmic learning theory developed in the framework of EFS's. We define two important classes of EFS's and a new hierarchy of various language classes. Then we discuss EFS's as logic programs. We show that EFS's form a good framework for inductive inference of languages by presenting model inference system for EFS's in Shapiro's sense. Using the framework we also show that inductive inference from positive data and PAC-learning are both much more powerful than they have been believed. We illustrate an application of our theoretical results to Molecular Biology.

This paper discusses a computer-aided network planning support system called PIGEON that has been developed primarily for advancing countries implementing the applicability to various types of networks and the supportability to the sensitivity analysis. For the implementation of the applicability, the customization by reflecting existing network facilities and their accompanying restrictive conditions into a design result is focused. A case study on the customization shows the effectiveness of the reflection. The procedures are given of the sensitivity analysis in order to examine and to evaluate the effect of the uncertain factors in network planning. In particular, a method called "network modification" is proposed for the sensitivity analysis for uncertain factors associated with a partial network. The network modification efficiently integrates network planner's judgments into a design result by the interactive method. In addition, this paper describes the importance of streamlining the data input and the evaluation of design results, showing the operating time required for each work phase in network planning.

The establishment of an intelligent network service operation architecture is important for facilitating development and integration of service operation systems. To do this, the basic concepts and goals of service operation items must first be clarified. Then, the necessary procedures as well as the required data on the behaviors of customers, operators and operation systems must be described. These various points are discussed based on an operation study methodology.

Over the past few years, the drive towards optimization and globalization of business activities has mandated the integration of various services, an increase in system scale, and the networking of a variety of systems. These requirements can only be satisfied by the introduction of systems that are able to accommodate and control multiple media and integrate LANs and PBXs synergistically. This paper proposes an architecture for next generation private networks called ANS (Areal Networking System) that is targeted at achieving flexible customization in an effort to meet a wide variety of user requirements as well as the ability to efficiently handle multimedia services. Based upon the clarification of various requirements on the ANS architecture, this paper defines two models for the ANS architecture. These models introduce modular building blocks in hierarchical structures that facilitate the custom design of networks. The key technologies for the ANS architecture are also discussed; for example, schemes for logically networking control functions by using virtual connections and a way to implement the LAN function.

The introduction of Integrated Services Digital Networks (ISDNs) poses a variety of new questions on telecommunications network design and planning. Furthermore, the formulation of traditional network design and planning problems need to be revisited in the ISDN context. This paper presents an overview of the recent progress and new challenges in developing ISDN design and planning methodologies that exploit revolutionary new telecommunications technologies. It will cover some important issues for ISDN design and planning, and will concentrate on three issues that are of particular importance: Design of networks with digital information transfer capabilities, design of networks with advanced network/traffic control techniques, and use of reliability objectives for network design and planning.

Parallel multiple context-free grammars (pmcfg's) and multiple context-free grammars (mcfg's) were introduced as extensions of context-free grammars to describe the syntax of natural languages. Pmcfg's and mcfg's deal with tuples of strings, and it has been shown that the universal recognition problem for mcfg's is EXP-POLY time-complete where the universal recognition problem is the problem to decide whether G generates w for a given grammar G and string w. In this paper, the universal recognition problems for the class of pmcfg's and for the subclass of pmcfg's with the information-lossless condition are shown to be EXP-POLY time-complete and PSPACE-complete, respectively. It is also shown that the problems for pmcfg's and for mcfg's with a bounded dimension are both -complete and those for pmcfg's and for mcfg's with a bounded degree are both -complete. As a corollary, the problem for modified head grammars introduced by Vijay-Shanker, et al. to define the syntax of natural languages is shown to be in deterministic polynomial time.

In the approximate learning model introduced by Valiant, it has been shown by Blumer et al. that an Occam algorithm is immediately a PAC-learning algorithm. An Occam algorithm is a polynomial time algorithm that produces, for any sequence of examples, a simple hypothesis consistent with the examples. So an Occam algorithm is thought of as a procedure that compresses information in the examples. Weakening the compressing ability of Occam algorithms, a notion of weak Occam algorithms is introduced and the relationship between weak Occam algorithms and PAC-learning algorithms is investigated. It is shown that although a weak Occam algorithm is immediately a (probably) consistent PAC-learning algorithm, the converse does not hold. On the other hand, we show how to construct a weak Occam algorithm from a PAC-learning algorithm under some natural conditions. This result implies the equivalence between the existence of a weak Occam algorithm and that of a PAC-learning algorithm. Since the weak Occam algorithms constructed from PAC-learning algorithms are deterministic, our result improves a result of Board and Pitt's that the existence of a PAC-learning algorithm is equivalent to that of a randomized Occam algorithm.

Network planning for a public switched telephone network is essentially the same as the company's business strategy. The social environment providing the market for communications services is undergoing rapid change in Japan as it evolves from an era of one basic mainstay service-namely, plain-old telephone service-to one in which a wide range of advanced new services are, or soon will be, available and there is fierce competition to provide those services. This paper covers some of the thinking behind NTT's strategy to put in place a flexible and effectual network that fully reflects the needs and desires of customers in this fast-changing environment.

This paper designs and evaluates highly parallel VLSI processors for real time 2-D state-space digital filters using hierarchical behavioral description language and synthesizer. The architecture of the 2-D state-space digital filtering system is a linear systolic array of homogeneous VLSI processors, each of which consists of eight processing elements (PEs) executing 1-D state-space digital filtering with multi-input and multi-output. Hierarchical behavioral description language and synthesizer are adopted to design and evaluate PE's and the VLSI processors. One 16 bit fixed-point PE executing a (4, 4)-th order 2-D state-space digital filtering is described on the basis of distributed arithmetic in about 1,200 steps by the description language and is composed of 15 K gates in terms of 2 input NAND gate. One VLSI processor which is a cascade connection of eight PEs is composed of 129 K gates and can be integrated into one 1515 [mm2] VLSI chip using 1 µm CMOS standard cell. The 2-D state-space digital filtering system composed of 128 VLSI processors at 25 MHz clock can execute a 1,0241,024 image in 1.47 [msec] and thus can be applied to real-time conventional video signal processing.