A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40 and +90. A low-IF receiver and direct-conversion transmitter architecture are employed. A temperature compensated receiver chain including a low-noise amplifier accomplishes a sensitivity of -90 dBm at frequency shift keying modulation even in the worst environmental condition. Design optimization of phase noise in a local oscillator and linearity of a power amplifier improves transmission signals and enables them to meet Bluetooth radio specifications. Fabrication in scaled 0.13 µm CMOS and operation at a low supply voltage of 1.5 V result in small area and low power consumption.

In this paper, we describe a bootstrapped nMOS switch that is modified to reduce leakage current for nMOS reversible energy recovery logic (nRERL) [1]. Conventional bootstrapped switches are not suitable for nRERL because they have nonadiabatic loss due to leakage current that flows while boosted. Therefore, we lowered the gate voltage of the isolation transistor in each bootstrapped switch to reduce this leakage current. With detailed analysis and simulation, we determined the range of the bias voltage, in which the switches can transfer full-swing input signals. We implemented a simple 8-bit nRERL microprocessor into silicon and measured its energy consumption to confirm our analysis. For the supply voltage of 1.8 V and the operating frequency of 880 kHz, we found that the microprocessor consumed about 8.5 pJ/cycle for 1.3 V < Vbias <1.6 V, which was just about a half of its energy consumption when Vbias = 1.7 V.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 µm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.

This paper analyzes the input-dependent sample-time error in MOS sampling circuits caused by the finite slope of the sampling clock, and clarifies the following: (i) Input-dependent sampling jitter causes phase modulation in the sampled data. (ii) The formulas for SDR due to such sampling errors are explicitly derived. (iii) NMOS sampling circuits generate even-order harmonics, which are greatly reduced by using a differential topology. (iv) CMOS sampling circuits without clock skew between Vclk and generate odd-order harmonics which a differential topology cannot help cancel, whereas circuits with clock skew generate even-order as well as odd-order harmonics. (v) For single-ended sampling circuits, the SDR of CMOS circuits without clock skew is better than that of NMOS circuits. (vi) NMOS differential sampling circuits are relatively insensitive to input-dependent sampling-time error effects, which would be the best regarding to the input-dependent sampling-time error effects. (vii) Its effects in case of NMOS differential samplers with finite skew between plus and minus path clocks are discussed. (viii) Its effects in CMOS samplers with finite skew between PMOS and NMOS clocks are discussed.

In this paper, bifurcation and chaotic behavior which occur in simple looped MOS inverters with high speed operation are described. The most important point in this work is to change a nonlinear transfer characteristic of a MOS inverter to the nonlinearity generating a chaos. Three types of circuits which include four, three and one MOS inverters, respectively, are proposed. A switched capacitor (SC) circuit to operate sampling holding is added in the loop in each of the circuits. The bifurcation and chaotic behavior have been found along with a variation of an external input, and/or a sampling clock frequency. The bifurcation and chaotic behavior of the proposed simple looped MOS inverters are verified by employing SPICE circuit simulator as well as the experiments. For the first type of four looped CMOS inverters, Lyapunov exponent λ which has the positive regions for the chaotic behavior can be calculated by use of the fitting nonlinear function synthesized from two sigmoid functions. For the second type of three looped CMOS inverters and the third type of one looped MOS inverter, the nonlinear charge/discharge characteristics of the hold capacitor in the SC circuit is utilized efficiently for forming the nonlinearity generating the bifurcation and chaotic behavior. Their bifurcation can be generated by the sampling clock frequency parameter which is controlled easily.