This letter deals with an iterative decoding algorithm (IDA) for product codes. In the IDA, a soft-input and output iterative bounded-distance and encoding-based decoding algorithm is used for the component codes. Simulation results over an AWGN channel with BPSK modulation is presented and show the effectiveness of the IDA.

The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.

In order to effectively improve the BER (Bit Error Rate) performance of noncoherent IR-UWB (Impulse Radio Ultra Wide Band) systems utilizing 2PPM (Binary Pulse Position Modulation), we propose a selective signal combining scheme which performs selective combination of received signals by estimating the SNR (Signal-to-Noise Ratio) of the energies during the pulse width interval.

This paper proposes a DCT-based steganographic method named StegErmelc in the JPEG domain. Three strategies are proposed, namely (i) edge-like block selection, (ii) recursive matrix encoding, and (iii) largest coefficient serving, to form a novel steganographic method for achieving scalable carrier capacity, low detectability by universal blind steganalyzer, and high image quality, simultaneously. For a given message length, StegErmelc flexibly scales its carrier capacity to accommodate the message while trading off with stego detectability. At full capacity, StegErmelc has comparable carrier capacity relative to the existing methods. When embedding the same amount of information, StegErmelc remarkably reduces the stego detection rate to about 0.3-0.5 lower than that of the existing methods considered, and consequently StegErmelc can withstand blind steganalyzer when embedding up to 0.10 bpc. Under the same condition, StegErmelc produces stego image with quality higher than that of the existing methods considered. Graphical comparison with three additional evaluation metrics is also presented to show the relative performance of StegErmelc with respect to the existing methods considered.

This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

A rectangular drawing is a plane drawing in which every face is a rectangle. In this paper we give a simple encoding scheme for rectangular drawings. Given a rectangular drawing R with maximum degree 3, our scheme encodes R with m + o(n) bits where n is the number of vertices of R and m is the number of edges of R. Also we give an algorithm to supports a rich set of queries, including adjacency and degree queries on the faces, in constant time.

We previously reported, for a coherent optical code division multiplexing (OCDM) system using fiber Bragg grating (FBG) phase en/decoders, that the signals exhibited phase shift tolerance for a difference between the light source wavelength and the Bragg wavelength of an FBG phase en/decoder when the two signals were multiplexed. However, the phase conditions of only the central wavelength among the ones forming a pulse were analyzed. For a more specific consideration, we calculated the phase of each wavelength forming the decoded pulse. In this report, the measured and calculated reflecting properties were compared and the reliability of the method was confirmed. We calculated the phase conditions of the decoded pulses and clarified the phase characteristics with regard to the phase modulation and the interference between pulses overlapped during decoding. For the realization of an asynchronous access, the FBG phase en/decoders should be designed so that the spreading time is the inverse of 2(texttransmission rate).

In networked control systems, uncontrollable events may unexpectedly occur in a plant before a proper control action is applied to the plant due to communication delays. In the area of supervisory control of discrete event systems, Park and Cho [5] proposed the notion of delay-nonconflictingness for the existence of a supervisor achieving a given language specification under communication delays. In this paper, we present the algebraic properties of delay-nonconflicting languages which are necessary for solving supervisor synthesis problems under communication delays. Specifically, we show that the class of prefix-closed and delay-nonconflicting languages is closed under intersection, which leads to the existence of a unique infimal prefix-closed and delay-nonconflicting superlanguage of a given language specification.

A fast algorithm to speed up the search process of vector quantization encoding is presented. Using the sum and the partial norms of a vector, some eliminating inequalities are constructeded. First the inequality based on the sum is used for determining the bounds of searching candidate codeword. Then, using an inequality based on subvector norm and another inequality combining the partial distance with subvector norm, more unnecessary codewords are eliminated without the full distance calculation. The proposed algorithm can reject a lot of codewords, while introducing no extra distortion compared to the conventional full search algorithm. Experimental results show that the proposed algorithm outperforms the existing state-of-the-art search algorithms in reducing the computational complexity and the number of distortion calculation.

In this paper, we investigated the effect of chromaticity and luminance of surround to decide subject neutral white, and conducted a mathematical model of adapting degree for environment. Factors for adapting degree consist of two parts, adapting degree of ambient chromaticity and color saturation. These can be applied to color appearance models (CAM), actually improve the performance of color matching of CAM, hence would produce the method of image reproduction to general display systems.

This paper presents a design of an asynchronous peer-to-peer half-duplex/full-duplex-selectable data-transfer system on-chip interconnected. The data-transfer method between channels is based on a 1-phase signaling scheme realized by using multiple-valued current-mode (MVCM) circuits and encoding, which performs high-speed communication. A data transmission is selectable by adding a mode-detection circuit that observes data-transmission modes; full-duplex, half-duplex and standby modes. Especially, since current sources are completely cut off during the standby mode, the power dissipation can be greatly reduced. Moreover, both half-duplex and full-duplex communication can be realized by sharing a common circuit except a signal-level conversion circuit. The proposed interface is implemented using 0.18-µm CMOS, and its performance improvement is discussed in comparison with those of the other ordinary asynchronous methods.

Conventional narrowband interference (NBI) rejection algorithms often assumed perfect pseudo-noise (PN) code synchronization. The functions of NBI rejection and code tracking are performed separately and independently by an adaptive filter and a code tracking loop, respectively. This paper presents two new receiver structures for direct sequence spread spectrum (DS/SS) systems, one operates in coherent mode and the other operates in noncoherent mode. Both receivers are designed to suppress NBI and minimize tracking jitter. Numerical results show that the proposed coherent receiver performs as good as the conventional receiver that uses an LMS NBI rejection filter with zero tracking jitter. The noncoherent receiver, when compared with the coherent one, suffers less than 3 dB degradation for bit error probability smaller than 10-3.

This paper deals with the scattering of a TM plane wave from a periodic grating with single defect, of which position is known. The surface is perfectly conductive and made up with a periodic array of rectangular grooves and a defect where a groove is not formed. The scattered wave above grooves is written as a variation from the diffracted wave for the perfectly periodic case. Then, an integral equation for the scattering amplitude is obtained, which is solved numerically by use of truncation and the iteration method. The differential scattering cross section and the optical theorem are calculated in terms of the scattering amplitude and are illustrated in figures. It is found that incoherent Wood's anomaly appears at critical angles of scattering. The physical mechanisms of Wood's anomaly and incoherent Wood's anomaly are discussed in relation to the guided surface wave excited by the incident plane wave. It is concluded that incoherent Wood's anomaly is caused by the diffraction of the guided surface wave.

Program analysis techniques have improved steadily over the past several decades, and software obfuscation schemes have come to be used in many commercial programs. A software obfuscation scheme transforms an original program or a binary file into an obfuscated program that is more complicated and difficult to analyze, while preserving its functionality. However, the security of obfuscation schemes has not been properly evaluated. In this paper, we analyze obfuscation schemes in order to clarify the advantages of our scheme, the XOR-encoding scheme. First, we more clearly define five types of attack models that we defined previously, and define quantitative resistance to these attacks. Then, we compare the security, functionality and efficiency of three obfuscation schemes with encoding variables: (1) Sato et al.'s scheme with linear transformation, (2) our previous scheme with affine transformation, and (3) the XOR-encoding scheme. We show that the XOR-encoding scheme is superior with regard to the following two points: (1) the XOR-encoding scheme is more secure against a data-dependency attack and a brute force attack than our previous scheme, and is as secure against an information-collecting attack and an inverse transformation attack as our previous scheme, (2) the XOR-encoding scheme does not restrict the calculable ranges of programs and the loss of efficiency is less than in our previous scheme.

A multiple-output function can be represented by a binary decision diagram for characteristic function (BDD_for_CF). This paper presents a method to represent multiple-output incompletely specified functions using BDD_for_CFs. An algorithm to reduce the widths of BDD_for_CFs is presented. This method is useful for decomposition of incompletely specified multiple-output functions. Experimental results for radix converters, adders, a multiplier, and lists of English words show that this method is useful for the synthesis of LUT cascades. An implementation of English words list by LUT cascades and an auxiliary memory is also shown.

A method of sequential circuit synthesis is proposed for Single-Flux-Quantum (SFQ) digital circuits. Since all logic gates of SFQ digital circuits are driven by a clock signal, methods of sequential circuit synthesis for semiconductor digital circuits cannot derive the full power of high-throughput computation of SFQ circuit technology. In the method, a 'state module' consisting of a DFF and several AND gates is used. First, states of a sequential machine are encoded by one-hot encoding and state modules are assigned to the states one-by-one, and then, the modules are connected with each other according to the state transition. For the connection, Confluence Buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high-throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for semiconductor digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average.

This paper proposes a method for reinforcing noun countability prediction, which plays a crucial role in demarcating correct determiners in machine translation and error detection. The proposed method reinforces countability prediction by introducing a novel heuristics called one countability per discourse. It claims that when a noun appears more than once in a discourse, all instances will share identical countability. The basic idea of the proposed method is that mispredictions can be corrected by efficiently using one countability per discourse heuristics. Experiments show that the proposed method successfully reinforces countability prediction and outperforms other methods used for comparison. In addition to its performance, it has two advantages over earlier methods: (i) it is applicable to any countability prediction method, and (ii) it requires no human intervention to reinforce countability prediction.

The key weakness of Low-Density Parity Check codes is the complexity of the encoding scheme. The generator matrices can be made by Gaussian elimination of parity check matrices for normal block codes. Richardson succeeded in making parity bits from parity check matrices by the low density computation. In this letter, we focus on the execution of numerical experiments which show that even if the matrix D, which is the part of the Richardson's LDPC matrix, is restricted, proposed LDPC codes is lower complexity than Richardson's LDPC codes. The constraint of D results in reducing complexity from O(n + g2) to O(n) due to the omission of computing inverse matrices of φ and T in Richardson's encoding scheme. All the sub-matrices in parity check matrix are composed of Circulant Permutation Matrices based on Galois Fields.

This paper proposes a new computational optimization method modified from the dynamic encoding algorithm for searches (DEAS). Despite the successful optimization performance of DEAS for both benchmark functions and parameter identification, the problem of exponential computation time becomes serious as problem dimension increases. The proposed optimization method named univariate DEAS (uDEAS) is especially implemented to reduce the computation time using a univariate local search scheme. To verify the algorithmic feasibility for global optimization, several test functions are optimized as benchmark. Despite the simpler structure and shorter code length, function optimization performance show that uDEAS is capable of fast and reliable global search for even high dimensional problems.

A new method for data hiding in binary images based on block pattern coding and dynamic programming with distortion-minimizing capabilities is proposed. Up to three message data bits can be embedded into each 22 block in an input image by changing the block's pixel pattern into another, which represents the value of the message data bits as a code according to a block pattern encoding table. And extraction of hidden message data is accomplished by block pattern decoding. To minimize the resulting image distortion, two optimization techniques are proposed. The first is to use multiple block pattern encoding tables, from which an optimal one is selected specifically for each input image, and the second is to use a dynamic programming algorithm to divide the message data into bit segments for optimal embedding in a sense of minimizing the number of binary bit flippings. Accordingly, not only more data bits can be embedded in an image block on the average, but the resulting image distortion is also reduced in an optimal way. Experimental results are also included to show the effectiveness of the proposed approach.