Self-encoded spread spectrum (SESS) derives its spreading codes from the random information source rather than using traditional pseudo-random codes. It has been shown that the memory in SESS modulated signals not only can deliver a 3 dB gain in additive white Gaussian noise (AWGN) channels, but also can be exploited to achieve time diversity and robust bit-error rate (BER) performance in fading channels. In this paper, we propose an extension to SESS, namely coded-sequence self-encoded spread spectrum (CS-SESS), and show that it can further improve the BER performance. We describe the CS-SESS scheme and present the theoretical analysis and simulation results for AWGN and fading channels. Iterative detector is developed to exploit the inherent temporal diversity of CS-SESS modulation. The simulation results show that it can achieve the expected 4.7 dB gain with a complexity that increases linearly with the spreading sequence length under AWGN. In Rayleigh fading channel, it can effectively mitigate the fading effects by exploiting the overall diversity gain. Chip interleaving is shown to yield a performance improvement of around 4.7 dB when compared to an chip interleaved direct sequence spread spectrum (DSSS) system.

Fast and accurate estimation of missing relations, e.g., similarity, distance and kernel, among objects is now one of the most important techniques required by major data mining tasks, because the missing information of the relations is needed in many applications such as economics, psychology, and social network communities. Though some approaches have been proposed in the last several years, the practical balance between their required computation amount and obtained accuracy are insufficient for some class of the relation estimation. The objective of this paper is to formalize a problem to quickly and efficiently estimate missing relations among objects from the other known relations among the objects and to propose techniques called “PSD Estimation” and “Row Reduction” for the estimation problem. This technique uses a characteristic of the relations named “Positive Semi-Definiteness (PSD)” and a special assumption for known relations in a matrix. The superior performance of our approach in both efficiency and accuracy is demonstrated through an evaluation based on artificial and real-world data sets.

In this paper, a method is proposed for reconstruction of the parameters of a non-binary block encoder using an intercepted sequence of noisy coded data. The proposed method is a generalization of the Barbier's method for the reconstruction of binary block codes to the more problematic case of non-binary codes. It has been shown mathematically that considering some revisions in definitions, such a generalization is possible. The proposed method is able to estimate the code parameters such as the code length, the code dimension, number of bits per symbol, and the dual-code subspace, and also to synchronize the sequence. Since the Reed-Solomon code is the most important type of non-binary block codes, an additional method is proposed to reconstruct the generator polynomial in the case of Reed-Solomon codes. The proposed method is evaluated via computer simulations which verify its strength and effectiveness.

In order to improve the detection performance in passive millimeter-wave (PMMW) imaging, a new method forwarding a null in the direction of human body and objects is proposed. The forward-nulling PMMW imaging using a dielectric tube occupied by cooling water placed near the focus line of a parabolic cylinder are performed. It is shown experimentally that the contrast between human body and conducting objects such as a conducting plate and a conducting sphere is improved by the presence of the cooling dielectric tube and parabolic cylinder.

In this paper, we survey the state of the art of the secure key exchange method that is secured by the laws of classical statistical physics, and involves the Kirchhoff's law and the generalized Johnson noise equation, too. We discuss the major characteristics and advantages of these schemes especially in comparison with quantum encryption, and analyze some of the technical challenges of its implementation, too. Finally, we outline some ideas about how to use already existing and currently used wire lines, such as power lines, phone lines, internet lines to implement unconditionally secure information networks.

An H.264/AVC encoder LSI (named “SARA”) that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains three motion estimation and compensation (ME/MC) engines with wide search ranges of -217.75 to +199.75 horizontally, -109.75 to +145.75 vertically, which can utilize almost all H.264/AVC ME/MC coding tools, such as multiple reference frame, variable block size, quarter-pel prediction, macroblock adaptive field/frame prediction (MBAFF), spatial/temporal direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2 dB to 1.7 dB higher than the JM. It was successfully fabricated in a 90-nm technology, and integrates 140 million transistors.

A new approach for encoding one class of quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. The proposed encoding method is applicable to parity-check matrices having dual-diagonal parity structure with single column of weight three in the parity generation region. Instead of finding the parity bits directly, the proposed method finds parity bits through vector correction. While the proposed LDPC encoding scheme is readily applicable to matrices defined in the IEEE physical layer standards, the computational complexity of the post processing operation for extraction of correction vector requires less effort than solving the linear equations involved with finding the parity bit as proposed by Myung et al.

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have several appealing properties regarding decoding, storage requirements and encoding aspects. In this paper, we focus on the QC LDPC codes over GF(q) whose parity-check matrices have fixed column weight j = 2. By investigating two subgraphs in the Tanner graphs of the corresponding base matrices, we derive two upper bounds on the minimum Hamming distance for this class of codes. In addition, a method is proposed to construct QC LDPC codes over GF(q), which have good Hamming distance distributions. Simulations show that our designed codes have good performance.

Recently, Haley and Grant introduced the concept of reversible codes – a class of binary linear codes that can reuse the decoder architecture as the encoder and encodable by the iterative message-passing algorithm based on the Jacobi method over F2. They also developed a procedure to construct parity check matrices of a class of reversible codes named type-I reversible codes by utilizing properties specific to circulant matrices. In this paper, we refine a mathematical framework for reversible codes based on circulant matrices through a ring theoretic approach. This approach enables us to clarify the necessary and sufficient condition on which type-I reversible codes exist. Moreover, a systematic procedure to construct all circulant matrices that constitute parity check matrices of type-I reversible codes is also presented.

This paper investigates the performance of a combination of the affine encoder and the maximum mutual information decoder for symmetric channels, and proves that the random coding error exponent can be attained by this combination even if the conditional probability of the symmetric channel is not known to the encoder and decoder. This result clarifies that the restriction of the encoder to the class of affine encoders does not affect the asymptotic performance of the universal code for symmetric channels.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.

Proving the security of cancelable biometrics and other template protection techniques is a key prerequisite for the widespread deployment of biometric technologies. BioEncoding is a cancelable biometrics scheme that has been proposed recently to protect biometric templates represented as binary strings like iris codes. Unlike other template protection schemes, BioEncoding does not require user-specific keys or tokens. Moreover, it satisfies the requirements of untraceable biometrics without sacrificing the matching accuracy. However, the security of BioEncoding against smart attacks, such as correlation and optimization-based attacks, has to be proved before recommending it for practical deployment. In this paper, the security of BioEncopding, in terms of both non-invertibility and privacy protection, is analyzed. First, resistance of protected templates generated using BioEncoding against brute-force search attacks is revisited rigorously. Then, vulnerabilities of BioEncoding with respect to correlation attacks and optimization based attacks are identified and explained. Furthermore, an important modification to the BioEncoding algorithm is proposed to enhance its security against correlation attacks. The effect of integrating this modification into BioEncoding is validated and its impact on the matching accuracy is investigated empirically using CASIA-IrisV3-Interval dataset. Experimental results confirm the efficacy of the proposed modification and show that it has no negative impact on the matching accuracy.

The dynamic encoding algorithm for searches (DEAS) is a recently developed algorithm that comprises a series of global optimization methods based on variable-length binary strings that represent real variables. It has been successfully applied to various optimization problems, exhibiting outstanding search efficiency and accuracy. Because DEAS manages binary strings or matrices, the decoding rules applied to the binary strings and the algorithm's structure determine the aspects of local search. The decoding rules used thus far in DEAS have some drawbacks in terms of efficiency and mathematical analysis. This paper proposes a new decoding rule and applies it to univariate DEAS (uDEAS), validating its performance against several benchmark functions. The overall optimization results of the modified uDEAS indicate that it outperforms other metaheuristic methods and obviously improves upon older versions of DEAS series.

Identifying the statistical independence of random variables is one of the important tasks in statistical data analysis. In this paper, we propose a novel non-parametric independence test based on a least-squares density ratio estimator. Our method, called least-squares independence test (LSIT), is distribution-free, and thus it is more flexible than parametric approaches. Furthermore, it is equipped with a model selection procedure based on cross-validation. This is a significant advantage over existing non-parametric approaches which often require manual parameter tuning. The usefulness of the proposed method is shown through numerical experiments.

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 3232, two 1616 or four 88 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.

Low-density parity-check (LDPC) codes are typically designed to avoid the length-4 cycles to ensure acceptable levels of performance. However, the turbo equalization, which relies on an interaction between an inner code such as an LDPC code and a soft-output Viterbi algorithm (SOVA) detector, exhibits a performance degradation due to the pseudo cycles. In this paper, we propose an interleaved modified array code (IMAC) that can reduce the number of pseudo cycles, hence, improving the gains from the iterative processing technique. The modification is made on the existing array-based LDPC codes named modified array codes (MAC) by introducing an additional interleaving matrix to the parity-check matrix. Simulation results on the perpendicular magnetic recording channels (PMRC) demonstrate that the IMAC outperforms both the MAC and the previously proposed random interleave array (RIA) codes for the partial-response targets under consideration. In addition, a subblock-based encoder design is proposed to reduce the encoding complexity of the IMAC and when compared with the RIA code, the IMAC exhibits a lower encoding complexity, and still maintains a comparable level of the decoding complexity.

This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.

We propose an efficient selective block encoding scheme with motion information feedback in distributed video coding (DVC). The proposed scheme estimates the spatial and temporal matching costs for each block in the side information (SI) and for the blocks with high matching costs, the motion information is provided to the encoder side to selectively encode the motion-compensated frame difference signal. Experimental results show that the proposed scheme outperforms the recently developed DVC algorithms.

This paper presents a non-interactive verifiable secret sharing scheme (VSS) tolerating a dishonest majority based on data pre-distributed by a trusted authority. As an application of this VSS scheme we present very efficient unconditionally secure protocols for performing multiplication of shares based on pre-distributed data which generalize two-party computations based on linear pre-distributed bit commitments. The main results of this paper are a non-interactive VSS, a simplified multiplication protocol for shared values based on pre-distributed random products, and non-interactive zero knowledge proofs for arbitrary polynomial relations. The security of the schemes is proved using the UC framework.

In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.