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[Keyword] OMP(3945hit)

3381-3400hit(3945hit)

  • Mobile Information Service Based on Multi-Agent Architecture

    Nobutsugu FUJINO  Takashi KIMOTO  Ichiro IIDA  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1401-1406

    This paper describes a mobile information access system based on a multi-agent architecture. With the rapid progress of wireless data communications, mobile Internet access will be more and more popular. In mobile environments, user location plays an important role for information filtering and flexible communication service. In this paper, we propose a mobile information service system where a user with a handy terminal accesses Internet in an open air to look up map information and related town information. Each user information is managed by an independent agent process. And the agent provides each user with a personal service collaborating with other applications. A map-based information service example based on this architecture is also described.

  • A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping

    Jie-Hong JIANG  Jing-Yang JOU  Juinn-Dar HUANG  Jung-Shian WEI  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1813-1819

    Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.

  • Vector Compaction Using Dynamic Markov Models

    Radu MARCULESCU  Diana MARCULESCU  Massoud PEDRAM  

     
    PAPER

      Vol:
    E80-A No:10
      Page(s):
    1924-1933

    This paper presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this paper introduces and characterizes a family of dynamic Markov trees that can model complex spatiotemporal correlations which occur during power estimation both in combinational and sequential circuits. As the results demonstrate, large compaction ratios of 1-2 orders of magnitude can be obtained without significant loss (less than 5% on average) in the accuracy of power estimates.

  • Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer

    Tadayuki SAKAKIBARA  Katsuyoshi KITAI  Tadaaki ISOBE  Shigeko YAZAWA  Teruo TANAKA  Yoshiko TAMAKI  Yasuhiro INAGAMI  

     
    PAPER-Computer Architecture

      Vol:
    E80-D No:9
      Page(s):
    925-932

    We propose an instruction-based variable priority scheme (IBVPS) which achieves high sustained memory throughput on a TCMP type vector supercomputer. Generally, there are two approaches to arbitrating interprocessor memory access conflict: request level priority control and fixed priority control. Each approach, however, affects performance in its own way: In the case of request level priority control, mutual obstruction causes a performance degradation, and in the case of fixed priority control, memory bank monopoly causes a performance degradation. Mutual obstruction refers to the interference among access requests coming from different instructions; memory bank monopoly refers to the un-interrupted accessing of the same memory bank by a series of higher priority instructions. The strategy of the instruction-based variable priority scheme consists in: (a) generally changing the priority assignment of all load/store pipelines at the end of any instruction running in the system, and (b) changing the priority assignment of all load/store pipelines more than once in the middle of an access instruction with a stride greater than 1 or an indirect access instruction which may monopolize some memory banks for an extended period of time. This strategy reduces mutual obstruction because the priority assignment is reshuffled for the entire group of load/store pipelines at a time. it also reduces memory bank monopoly because the opportunity for memory access is made equal among different instructions by changing the priority assignment at the end of an instruction. Moreover, it prevents the memory bank monopoly by a memory access instruction with a stride greater than 1 or an indirect access instruction, by changing the priority assignment more frequently. Consequently, high sustained memory throughput is achieved on TCMP type vector supercomputers.

  • Multi-clustering Network for Data Classification System

    Rafiqul ISLAM  Yoshikazu MIYANAGA  Koji TOCHINAI  

     
    PAPER-Digital Signal Processing

      Vol:
    E80-A No:9
      Page(s):
    1647-1654

    This paper presents a new multi-clustering network for the purpose of intelligent data classification. In this network, the first layer is a self-organized clustering layer and the second layer is a restricted clustering layer with a neighborhood mechanism. A new clustering algorithm is developed in this system for the efficiently use of parallel processors. This parallel algorithm enables the nodes of this network to be independently processed in order to minimize data communication load among processors. Using the parallel processors, the quite low calculation cost can be realized among the conventional networks. For example, a 4-processor parallel computing system has shown its ability to reduce the time taken for data classification to 26.75% of a single processor system without declining its performance.

  • Implementaion of Active Complex Filter with Variable Parameter Using OTAs

    Xiaoxing ZHANG  Xiayu NI  Masahiro IWAHASHI  Noriyoshi KAMBAYASHI  

     
    LETTER-Analog Signal Processing

      Vol:
    E80-A No:9
      Page(s):
    1721-1724

    In this paper, implementation of a first-order active complex filter with variable parameter using operational transconductance amplifiers (OTAs) and grounded copacitors is presented. The proposed configurations can be used as s key building block to realize high-order active complex filters with variable parameter in cascade and leapfrog configuration. Experimental results which are in good agreement with theoretical responses are also given o demonstrate the feasibility of the proposed configurations.

  • A Massive Digital Neural Network for Total Coloring Problems

    Nobuo FUNABIKI  Junji KITAMICHI  Seishi NISHIKAWA  

     
    LETTER

      Vol:
    E80-A No:9
      Page(s):
    1625-1629

    A neural network of massively interconnected digital neurons is presented for the total coloring problem in this paper. Given a graph G (V, E), the goal of this NP-complete problem is to find a color assignment on the vertices in V and the edges in E with the minimum number of colors such that no adjacent or incident pair of elements in V and E receives the same color. A graph coloring is a basic combinatorial optimization problem for a variety of practical applications. The neural network consists of (N+M) L neurons for the N-vertex-M-edge-L-color problem. Using digital neurons of binary outputs and range-limited non-negative integer inputs with a set of integer parameters, our digital neural network is greatly suitable for the implementation on digital circuits. The performance is evaluated through simulations in random graphs with the lower bounds on the number of colors. With a help of heuristic methods, the digital neural network of up to 530, 656 neurons always finds a solution in the NP-complete problem within a constant number of iteration steps on the synchronous parallel computation.

  • The Improved Quasi-Minimal Residual Method on Massively Parallel Distributed Memory Computers

    Tianruo YANG  Hai Xiang LIN  

     
    PAPER-Computer Architecture

      Vol:
    E80-D No:9
      Page(s):
    919-924

    For the solutions of linear systems of equations with unsymmetric coefficient matrices, we propose an improved version of the quasi-minimal residual (IQMR) method by using the Lanczos process as a major component combining elements of numerical stability and parallel algorithm design. For Lanczos process, stability is obtained by a coupled two-term procedure that generates Lanczos vectors scaled to unit length. The algorithm is derived such that all inner products and matrixvector multiplications of a single iteration step are independent and communication time required for inner product can be overlapped efficiently with computation time. Therefore, the cost of global communication on parallel distributed memory computers can be significantly reduced. The resulting IQMR algorithm maintains the favorable properties of the Lanczos process while not increasing computational costs. The efficiency of this method is demonstrated by numerical experimental results carried out on a massively parallel distributed memory computer, the Parsytec GC/PowerPlus.

  • Scalable Parallel Memory Architecture with a Skew Scheme

    Tadayuki SAKAKIBARA  Katsuyoshi KITAI  Tadaaki ISOBE  Shigeko YAZAWA  Teruo TANAKA  Yasuhiro INAGAMI  Yoshiko TAMAKI  

     
    PAPER-Computer Architecture

      Vol:
    E80-D No:9
      Page(s):
    933-941

    We present a scalable parallel memory architecture with a skew scheme by which permanent-concentration-free strides, if any, do not depend on the number of ways in parallel memory interleaving. The permanent-concentration is a kind of memory access conflict. With conventional skew schemes, permanent-concentration-free strides depended on the number of banks (or bank groups) in parallel memory (=number of ways in parallel memory interleaving). We analyze two kinds of cause of conflicts: permanent-concentration occurs when memory access requests concentrate in limited number of banks (or bank groups) in parallel memory, and transient-concentration, when memory access requests transiently concentrate in some banks (or bank groups) in parallel memory. We have identified permanent-concentration-free strides, which are independent of the number of banks (or bank groups) in parallel memory, by solving two concentrations separately. The strategy is to increase the size of address block of shifting address assignment to the parallel memory in order to reduce permanent-concentrations, and make the size of the buffer for each banks (or bank groups) in the parallel memory match the size of address block of shifting in order to absorb transient-concentrations. The skew scheme uses the same size of address block of shifting address assignment for memory systems for different numbers of banks (or bank groups) in parallel memory. As a result, scalability for permanent-concentration-free strides is achieved independent of the number of banks (or bank groups) in parallel memory.

  • A Novel Replication Technique for Detecting and Masking Failures for Parallel Software: Active Parallel Replication

    Adel CHERIF  Masato SUZUKI  Takuya KATAYAMA  

     
    PAPER-Fault Tolerance

      Vol:
    E80-D No:9
      Page(s):
    886-892

    We present a novel replication technique for parallel applications where instances of the replicated application are active on different group of processors called replicas. The replication technique is based on the FTAG (Fault Tolerant Attribute Grammar) computation model. FTAG is a functional and attribute based model. The developed replication technique implements "active parallel replication," that is, all replicas are active and compute concurrently a different piece of the application parallel code. In our model replicas cooperate not only to detect and mask failures but also to perform parallel computation. The replication mechanisms are supported by FTAG run time system and are fully application-transparent. Different novel mechanisms for checkpointing and recovery are developed. In our model during rollback recovery only that part of the computation that was detected faulty is discarded. The replication technique takes full advantage of parallel computing to reduce overall computation time.

  • TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing

    Vijay K. JAIN  Tadasse GHIRMAI  Susumu HORIGUCHI  

     
    PAPER-Interconnection Networks

      Vol:
    E80-D No:9
      Page(s):
    837-846

    Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.

  • An Improved Technique to Measure Nonlinear Phase Shift and Amplitude Distortion

    Naoki HONDA  Takashi KOMAKINE  Kazuhiro OUCHI  

     
    PAPER

      Vol:
    E80-C No:9
      Page(s):
    1194-1202

    A modified frequency domain method for analyzing nonlinear waveform distortion in a magnetic recording process is presented. The measurement technique combines a 5th harmonic measurement technique, which uses a specific 30-bit pattern including dibits, and a precompensation technique for the dibits. The 5th harmonic voltage ratio given by the former technique includes the amount of NLTS (Nonlinear transition shift) and PE (Partial erasure) in dibits. The latter precompensation technique is employed to evaluate the PE as the minimum in the 5th harmonic voltage ratio. The true NLTS can be estimated from the amount of distortion and the evaluated PE. The high accuracy of the technique was confirmed by an examination using a pulse pattern generator with varied phase and amplitude. Finally, the effects of medium properties such as coercivity and squareness on the nonlinear distortions have been investigated by applying the technique to particulate flexible media. The NLTS increased with squareness from 3.5% to 7% while PE was less than 6% for any squareness at a recording density of 76 kFRPI. When coercivity became large, NLTS and PE decreased. The direction of NLTS for Ba-ferrite media agreed with that for a perpendicular Co-Cr thin-film medium.

  • A Digital Neural Network for Multilayer Channel Routing with Crosstalk Minimization

    Nobuo FUNABIKI  Junji KITAMICHI  Seishi NISHIKAWA  

     
    PAPER-Neural Networks

      Vol:
    E80-A No:9
      Page(s):
    1704-1713

    A digital neural network approach is presented for the multilayer channel routing problem with the objective of crosstalk minimization in this paper. As VLSI fabrication technology advances, the reduction of crosstalk between interconnection wires on a chip has gained important consideration in VLSI design, because of the closer interwire spacing and the circuit operation at higher frequencies. Our neural network is composed of N M L digital neurons with one-bit output and seven-bit input for the N-net-M-track-2L-layer problem using a set of integer parameters, which is greatly suitable for the implementaion on digital technology. The digital neural network directly seeks a routing solution of satisfying the routing constraint and the crosstalk constraint simultaneously. The heuristic methods are effectively introduced to improve the convergence property. The performance is evaluated through solving 10 benchmark problems including Deutsch difficult example in 2-10 layers. Among the existing neural networks, the digital neural network first achieves the lower bound solution in terms of the number of tracks in any instance. Through extensive simulation runs, it provides the best maximum crosstalks of nets for valid routing solutions of the benchmark problems in multilayer channels.

  • High-Speed Protective Packaging of Fusion Splices Using an Internal Heat Source

    Mitsutoshi HOSHINO  Norio MURATA  

     
    PAPER-Communication Cable and Wave Guides

      Vol:
    E80-B No:9
      Page(s):
    1321-1326

    Materials for a new reinforcement method using an internal heating technique have been developed experimentally for fusion splices. The method employs a protective package of a carbon-fiber composite and a hot-melt adhesive in a heat-shrinkable tube. The most appropriate heating current and heating time were determined from a consideration of the decomposition temperature of the adhesive (300) and the complete shrinking temperature (115) and the minimum welding temperature of Nylon 12 (about 180). The protective package can be installed in less than 30 seconds at a power of 10 W. Air bubbles which might cause microbending were completely eliminated by using Nylon 12 as the hot-melt adhesive, irradiated polyethylene as the heat-shrinkable tube and a carbon-fiber-composite electrical heating rod which also acted a tension member. The key for preparing the carbon-fiber composite was to remove its impurities. Under the condition of temperature difference larger than 40 deg. between the shrinking temperature of the heat-shrinkable tube and the melting temperature of the hot-melt adhesive. Nylon 12 and irradiated polyethylene were needed for the complete elimination of residual bubbles. By using Nylon 12 as the hot-melt adhesive, a reliable protective package could be achieved for a fusion spliced optical fiber with a low excess loss of less than 0.06 dB/splice between -60 and +70 and a high tensile strength of 3.9 kg.

  • Neural Network Based Photometric Stereo with a Nearby Rotational Moving Light Source

    Yuji IWAHORI  Robert J. WOODHAM  Masahiro OZAKI  Hidekazu TANAKA  Naohiro ISHII  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E80-D No:9
      Page(s):
    948-957

    An implementation of photometric stereo is described in which all directions of illumination are close to and rotationally symmetric about the viewing direction. THis has practical value but gives rise to a problem that is numerically ill-conditioned. Ill-conditioning is overcome in two ways. First, many more than the theoretical minimum number of images are acquired. Second, principal components analysis (PCA) is used as a linear preprocessing technique to determine a reduced dimensionality subspace to use as input. The approach is empirical. The ability of a radial basis function (RBF) neural network to do non-parametric functional approximation is exploited. One network maps image irradiance to surface normal. A second network maps surface normal to image irradiance. The two networks are trained using samples from a calibration sphere. Comparison between the actual input and the inversely predicted input is used as a confidence estimate. Results on real data are demonstrated.

  • Perfect Reconstruction Two-CH Linear Phase IIR Filter Bank with Quasi Power Complementary Characteristic

    Shuitsu MATSUMURA  Fumihiko MURATA  Tsuyoshi TAKEBE  

     
    PAPER

      Vol:
    E80-A No:8
      Page(s):
    1403-1409

    This paper describes a design technique of perfect reconstruction (PR) two-channel IIR filter bank. M.J.T. Smith et al., gave two types of PR IIR filter bank systems. One is the system such that the analysis and synthesis filters with nonlinear phase are implemented with all-pass polyphase filters and satisfy the power complementary condition approximately. The other is the system such that all the analysis and synthesis filters have liner phase responses and do not satisfy the power complementary condition. To improve coding performance, we propose a filter bank system such that all the analysis and synthesis filters have linear phase and satisfy the power complementary condition approximately.

  • A Novel FEC Scheme for Differentially Detected QPSK Signals in Mobile Computing Using High-Speed Wireless Access

    Takatoshi SUGIYAMA  Masahiro UMEHIRA  

     
    PAPER

      Vol:
    E80-B No:8
      Page(s):
    1153-1159

    This paper proposes a novel FEC (forward error correction) scheme for high-speed wireless systems aiming at mobile computing applications. The proposed scheme combines inner nonredundant error correction with outer parallel encoding random FEC for differentially detected QPSK (quadrature phase shift keying) signals. This paper, first, examines error patterns after the differential detection with nonredundant error correction and reveals that particular double symbol errors occur with relatively high probability. To improve the outer FEC performance degradation due to the double symbol errors, the proposed scheme uses I and Q channel serial to parallel conversion in the transmission side and parallel to serial conversion in the receiving side. As a result, it enables to use simple FEC for the outer parallel encoding random FEC without interleaving. Computer simulation results show the proposed scheme employing one bit correction BCH coding obtains a required Eb/No improvement of 1.2 dB at a Pe of 10-5 compared to that with the same memory size interleaving in an AWGN environment. Moreover, in a Rician fading environment where directional beam antennas are assumed to be used to improve the degradation due to severe multipath signals, an overall Eb/No improvement at Pe of 10-5 of 3.0 dB is achieved compared to simple differential detection when the condition of delay spread of 5 nsec, carrier to multipath signal power ratio of 20 dB and Doppler frequency at 20 GHz band of 150 Hz.

  • Fingerprint Compression Using Wavelet Packet Transform and Pyramid Lattice Vector Quantization

    Shohreh KASAEI  Mohamed DERICHE  Boualem BOASHASH  

     
    PAPER

      Vol:
    E80-A No:8
      Page(s):
    1446-1452

    A new compression algorithm for fingerprint images is introduced. A modified wavelet packet scheme which uses a fixed decomposition structure, matched to the statistics of fingerprint images, is used. Based on statistical studies of the subbands, different compression techniques are chosen for different subbands. The decision is based on the effect of each subband on reconstructed image, taking into account the characteristics of the Human Visual System (HVS). A noise shaping bit allocation procedure which considers the HVS, is then used to assign the bit rate among subbands. Using Lattice Vector Quantization (LVQ), a new technique for determining the largest radius of the Lattice and its scaling factor is presented. The design is based on obtaining the smallest possible Expected Total Distortion (ETD) measure, using the given bit budget. At low bit rates, for the coefficients with high-frequency content, we propose the Positive-Negative Mean (PNM) algorithm to improve the resolution of the reconstructed image. Furthermore, for the coefficients with low-frequency content, a lossless predictive compression scheme is developed. The proposed algorithm results in a high compression ratio and a high reconstructed image quality with a low computational load compared to other available algorithms.

  • A Note on the Complexity of k-Ary Threshold Circuits

    Shao-Chin SUNG  Kunihiko HIRAISHI  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E80-D No:8
      Page(s):
    767-773

    Obradovic and Parberry showed that any n-input k-ary function can be computed by a depth 4 unit-weight k-ary threshold circuit of size O(nkn). They also showed that any n-input k-ary symmetric function can be computed by a depth 6 unit-weight k-ary threshold circuit of size O(nk+1). In this paper, we improve upon and expand their results. The k-ary threshold circuits of nonunit weight and unit weight are considered. We show that any n-input k-ary function can be computed by a depth 2 k-ary threshold circuit of size O(kn-1). This means that depth 2 is optimal for computing some k-ary functions (e.g., a PARITY function). We also show that any n-input k-ary function can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(kn). Next, we show that any n-input k-ary symmetric function can be computed by a depth 3 k-ary threshold circuit of size O(nk-1), and can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(knk-1). Finally, we show that if the weights of the circuit are polynomially bounded, some k-ary symmetric functions cannot be computed by any depth 2 k-ary threshold circuit of polynomial-size.

  • Digitalization of Mobile Communication Systems

    Heiichi YAMANOTO  

     
    INVITED PAPER

      Vol:
    E80-B No:8
      Page(s):
    1111-1117

    Recently, the number of users utilizing mobile communication services has increased greatly in many information and communication fields. In the future, the number of mobile communication system users will increase even faster, until the rate of diffusion ultimately reaches that of telephones. The day that each person has his own portable mobile terminal is not so far off. Moreover, the systems will not only be used as telephones but also as mobile computing for multimedia information. Digitalization technologies of mobile communication systems needed to realize such mobile computing will be introduced in this paper.

3381-3400hit(3945hit)