In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

The reallocation problem is defined as determining whether products can be moved from their current storehouses to their target storehouses in a number of moves that is less than or equal to a given number. This problem is defined simply and has many practical applications. We previously presented necessary and sufficient conditions whether an instance of the reallocation problem is feasible, as well as a linear-time algorithm that determines whether aall products can be moved, when the volume of the products is restricted to one. However, a linear-time algorithm that generates the order of moving the products has not been reported yet. Such an algorithm is proposed in this paper. We have also previously proved that the reallocation problem is NP-complete in the strong sense when the volume of the products is not restricted and the products have evacuation storehouses show that the reallocation problem is NP-complete in the strong sense even when none of the products has evacuation storehouses.

The present paper clarifies that the variance of the maximum likelihood estimator (MLE) of a parameter does not reach the Cramer-Rao lower bound (CRLB) when fitting a straight-line to observed two-dimensional data. In addition, the variance of the MLE can be shown to be equal to the CRLB only if observed noise reduces to a one-dimensional Gaussian variable. For most practical applications, it can be assumed that noise is added only to the range direction. In this case, the MLE is clearly an asymptotically effective estimator. However, even if we assume such a noise model, ML line-fitting to the data from many points of view has a high computational cost. The present paper proposes an alternative fitting method in order to provide a cost-effective unbiased estimator. The reliability of this new method is analyzed statistically and by computer simulation.

Competition in some telecommunication services has emerged in Japan since deregulation of telecommunication markets in 1985. Demand forecasting methods which take into account competition and investment plan based on it should be studied. There are many forecasting and network planning methods, but most of them do not take into account competition. Thus, in this paper, the competitive Bass model, attraction model, regression model and entropy model are discussed as forecasting methods which can be used under competitive environment. Most of the existing planning methods have treated costs and interest rates as deterministic values, but in fact they are not deterministic. Thus, we show a method which represents undefined factors by fuzzy numbers with triangular membership functions.

This paper presents algorithms for computing the Minkowski sum of two polygons P and Q for a family of problems. For P being convex and Q being monotone, an algorithm is given with O (nm) time and space complexity. For both P and Q being monotone polygons, an O (nm log nm) time algorithm is presented and it is shown that the complexity of the sum is Θ (nmα(min(n,m))) in the worst case, where α() is the inverse of Ackermann's function. Finally, an O ((nm+k)log nm) time complexity algorithm is given when P is monotone and Q is simple, where k in the worst case could be Θ(n2m). The complexity of P Q is shown to be Θ(n2m) in the worst case. Here, m and n denote the number of edges of P and Q, respectively.

We show that the truth of a prenex normal form Presburger sentence bounded only by existential quantifiers (or an EPP-sentence) involving two variables can be decided in deterministic polynomial time. Specifically, an upper bound of the computation for the decision is O(n3u), where n is the number of atoms of the EPP-sentence, and u is the largest absolute value of all coefficients in the EPP-sentence. In the analysis for the upper bound, the random access machine is assumed for the machine model. Additionally, a uniform cost criterion is assumed. Deciding the truth of an EPP-sentence is an NP-complete problem, when the number of variables is not fixed. Furthermore, whether the truth of an EPP-sentence involving two or more variables can be decided in deterministic polynomial time, when the number of variables is fixed, or not has remained an open problem. We previously proposed a procedure for quickly deciding the truth of an EPP-sentence on the basis of a suggestion by D.C.Cooper. We found the upper bound by analyzing the decision procedure. The procedure can be applied to both automated correctness proof of specification in various design fields and detection of infeasible paths in a program. In the procedure, a matrix denoting coefficients of the variables in the EPP-sentence is triangulated.

A CMOS programmable gain amplifier (PGA) with a swiched capacitor offset compensation circuit is described. The mean compensation error is 130µV at the input, and the standard deviation of the compensation error is 50µV. This PGA is applicable to a baseband amplifier for digital radio communication terminals.

Force curves obtained from an elastic contact theory are shown and compared with experimental results. In the elastic contact theory, a pin-on-disk contact is assumed and the following interaction are taken into consideration; (i) elastic deformation, (ii) the specific energy of adhesion in the area of the contact, which is expressed as the difference between the surface energies and the interface energy, (iii) the long-range interaction outside the area of contact, assuming the additivity of the Lennard-Jones type potential, and (iv) another elastic term for the measurement system such as the cantilever stiffness of an atomic force microscope (AFM). In the limit when the stiffness is infinite, the theory conforms to Muller-Yushchenko-Derjaguin (MYD) theory. In the limit when the surface-surface interaction is negligible, the theory conforms to the analytical theory by Takahashi-Mizuno-Onzawa. In the limit when the stiffness is infinite and the long-range interaction outside the area of contact is negligible, the theory conforms to Johnson-Kendall-Roberts (JKR) theory. All parameters and all equations are normalized and the normalized force curve is obtained as the functional of only two parameters; (1) the normalized stiffness of the measurement system, and (2) the normalized distance which is used in the expression of the Lennard-Jones potential. The force-displacement plots are converted into force-penetration plots.

A formal system-level synthesis model for the concurrent object-oriented design of parallel computer systems, called Multi-token Object-oriented Bi-directional net (MOBnet), is proposed. The MOBnet model extends the standard Petri net by defining (1) multiple tokens to represent different kinds of synthesis control information, (2) object-oriented nodes (places) to denote the system parts under synthesis, and (3) bi-directional arcs to model the design completion check and synthesis rollback operations. In this paper, we first show that MOBnet can serve as a pre-fabrication design methodology analysis tool in ways such as class hierarchy construction, design specification comparison, reachability analysis, and concurrent process management and analysis. We then formally prove MOBnet to be a valid model for concurrent synthesis and give experimental application examples to verify. Finally, solution schemes for the design completion check and synthesis rollback problems are formally validated by analyzing the dynamic behavior of MOBnet, and experimentally illustrated through examples.

This paper proposes the concept of information retrieval for fine arts database system on the fuzzy set theory, especially concerning to sensitive impression and location data. The authors have already reported several important formulations about the data structure and information retrieval models based on the fuzzy set theory for multimedia database. The fuzzy models of the information retrieval are implemented in the fine arts database system, which has the following features: (1) The procedure of information retrieval is formulated in the fuzzy set theory; (2) This database can treat multimedia data such as document data, sensitive impression, location information, and imagedata. (3) It is possible to retrieve the stored data based on sensitive impression and the location data such as "joyful pictures which have a mountain in the center and there is a tree in the right"; (4) Users can input impression words as a retrieval condition, and estimate their grades such as "low," "medium," and "high"; (5) For the result of information retrieval, the satisfaction grade is calculated based on fuzzy retrieval model; and (6) The stored data are about 400 fine arts paintings which are inserted by the textbook of fine arts currently used at the junior high school and high school in Japan. These features of this system give an effects of the fine arts education, and should be useful for information retrieval of fine arts. The results of this study will become increasingly important in connection with development of multimedia technology.

We developed the computer calligraphy, that is, a computer formation of brush-written Kanji characters using calligraphic knowledge. The style of brush handwriting depends mainly on the way of using a writing brush. Brush writing skills include the direction of brush at the beginning, curvature and turning the brush, the brush-up at the termination point in a stroke. We make up the calligraphic knowledge base according to the above mentioned brush writing skills. For simulating real brush movement, we represent the brush contact form that is the brush shape on the writing plane as a brush-touch. The system can control the size and direction of this brush-touch during the brush simulation. The system simulates the real brush writing to move the brush-touch along the skeleton letter shape in the standard database. We get the brush written Kanji from the locus of the brush-touch movement. We can extend this system to the new on line training system for brush writing using the simulation of brushtouch movement modified by the pressure, speed and rotation of the writing brush, and the skeleton letters written by a learner from the tablet. This system is also useful for students learning how to write Japanese letters beautifully with brush.

This paper presents an analog 2-dimensional discrete cosine transform (2-D DCT) processor for focal-plane image compression. The on-chip analog 2-D DCT processor can process directly the analog signal of the CMOS image sensor. The analog-to-digital conversion (ADC) is preformed after the 2-D DCT, and this leads to efficient AD conversion of video signals. Most of the 2-D DCT coefficients can be digitized by a relatively low-resolution ADC or a zero detector. The quantization process after the 2-D DCT can be realized by the ADC at the same time. The 88-point analog 2-D DCT processor is designed by switched-capacitor (SC) coefficient multipliers and an SC analog memory based on 0.35µm CMOS technology. The 2-D DCT processor has sufficient precision, high processing speed, low power dissipation, and small silicon area. The resulting smart image sensor chips with data compression and digital transmission functions are useful for the high-speed image acquisition devices and portable digital video camera systems.

This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

Recently, computer communications, especially Internet services, have become popular and as a result, high-speed network access circuits are now desired. NTT has developed an economical and high-speed multimedia computer network, combining satellite and terrestrial circuits. The satellite circuit transmission rate is approximately 30-Mbit/s. To select IP packets from such high-speed satellite circuits, this system employs the asynchronous transfer mode (ATM) in the satellite section and we have developed a new economical satellite circuit receive adapter (SRA) for the satellite section. This paper describes the system configurations and the key network control technologies for multi-link routing, high speed processing and broadcasting.

Recently two interesting conjectures on the linear complexity of binary complementary sequences of length 2nN0 were given by Karkkainen and Leppanen when those sequences are considered as periodic sequences with period 2nN0, where those sequences are constructed by successive concatenations or successive interleavings from a pair of kernel complementary sequences of length N0. Their conjectures were derived from numerical examples and suggest that those sequences have very large linear complexities. In this paper we give the exact formula of characteristic polynomials for those complementary sequences and show that their conjectures are true.

The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.

The Hopfield neural network for optimization problems often falls into local minima. To escape from the local minima, the neuron unit in the neural network is modified to become an oscillatory unit by adding a simple self-feedback circuit. By combining the oscillatory unit with an energy-value extraction circuit, an oscillatory neural network is constructed. The network can repeatedly extract solutions, and can simultaneously evaluate them. In this paper, the network is applied to four NP-complete problems to demonstrate its generality and efficiency. The network can solve each problem and can obtain better solutions than the original Hopfield neural network and simple algorithms.