Predicting the performance of high speed wide area ATM networks (WANs) is a difficult task. Evaluating the performance of these systems by means of mathematical models is not yet feasible. As a result, the creation of simulation models is usually the only means of predicting and evaluating the performance of such systems. In this paper, we use measurements to validate simulation models of TCP/IP over high speed ATM wide area networks. Validation of simulations with measurements is not common; however, it is needed so that simulation models can be used with confidence to accurately characterize the performance of ATM WANs. In addition, the appropriate level of complexity of the simulation models needs to be determined. The results show that under appropriate conditions simulation models can accurately predict the performance of complex high speed ATM wide area networks. This work also shows that the user perceived performance is dependent on host processing demands.

This correspondence reports novel computationally efficient algorithms for multiplication of bicomplex numbers, which belong to hypercomplex numbers. The proposed algorithms require less number of real multiplications than existing methods. Furthermore, they give more effective implementation when applied to constant coefficient digital filters.

Electroabsorption modulators are high speed devices that are rapidly being commercialised and finding applications in a number of areas, particularly in telecommunications. A CW laser diode modulated by an electroabsorption modulator constitutes an extremely stable, robust and simple source of high quality, high repetition rate ultrashort optical pulses. In this paper we describe the capabilities and limitations of such pulse sources, and present nonlinear pulse compression and manipulation techniques that allow one to overcome these limitations. We also present the design of a new class of comb-like dispersion-profiled fibre compressor. Such a compressor is easily fabricated from commercially available fibres and represents a simple yet powerful way of extending the range of pulse durations available. As the electroabsorption modulator is essentially a high speed switch it is also applicable to optical processing problems, and we report the application of such a device to demultiplexing.

The timing jitter of the optical pulse from a gain-switched laser diode is reduced by CW light injection. The reduction ratio of the timing jitter is 5. 5. The pulse width was compressed by a nonlinear optical loop mirror to a pedestal-free optical pulse with a pulse width of 420 fs.

This paper summarizes our recent efforts in modelocking Ti:sapphire lasers with semiconductor saturable absorber mirrors (SESAMs). We present the shortest optical pulses ever generated directly from a laser. The modelocking build-up time (T BU) of 60 µs is, to our knowledge, the shortest reported for a passively modelocked KLM laser to date.

In this paper, two universal building blocks for complex filter using CCIIs, CFCCIIs, grounded resistors and grounded capacitors are presented. These can be used to realize various complex bandpass filters with arbitrary order. The paper shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of the conventional one employing op-amps, and that the sensitivities for all components are relatively small. Experimental results are used for verifying the validity of the proposed circuits.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.

A simple method of compensating the DC drift of LiNbO3 Mach-Zehnder intensity modulators for very high speed optical transmission systems is proposed. This method adds low frequency perturbation to the modulator driving signal, and controls the bias voltage using the detected envelope of the modulator output signal. The control circuit is successfully demonstrated to work with less than a 0. 1-dB power penalty.

This paper focuses on competitive learning algorithms for WTA (winner-take-all) networks which perform rotation invariant pattern classification. Although WTA networks may theoretically be possible to achieve rotation invariant pattern classification with infinite memory capacities, actual networks cannot memorize all input data. To effectively memorize input patterns or the vectors to be classified, we present two algorithms for learning vectors in classes (LVC1 and LVC2), where the cells in the network memorize not only weight vectors but also their firing numbers as statistical values of the vectors. The LVC1 algorithm uses simple and ordinary competitive learning functions, but it incorporates the firing number into a coefficient of the weight change equation. In addition to all the functions of the LVC1, the LVC2 algorithm has a function to utilize under-utilized weight vectors. From theoretical analysis, the LVC2 algorithm works to minimize the energy of all weight vectors to form an effective memory. From computer simulation with two-dimensional rotated patterns, the LVC2 is shown to be better than the LVC1 in learning and generalization abilities, and both are better than the conventional Kohonen self-organizing feature map (SOFM) and the learning vector quantization (LVQ1). Furthermore, the incorporation of the firing number into the weight change equation is shown to be efficient for both the LVC1 and the LVC2 to achieve higher learning and generalization abilities. The theoretical analysis given here is not only for rotation invariant pattern classification, but it is also applicable to other WTA networks for learning vector quantization.

Though causal order of message delivery simplifies the design and development of distributed applications, the overhead of enforcing it is not negligible. We claim that a causal order algorithm which does not send any redundant information is efficient in the sense of communication overhead. We characterize and classify the redundant information into four categories: information regarding just delivered, already delivered, just replaced, and already replaced messages. We propose an efficient causal multicast algorithm which prevents propagation of these redundant information. Our algorithm sends less amount of control information needed to ensure causal order than other existing algorithms and can also be applied to systems whose communication channels are not FIFO. Since our algorithm's communication overhead increases relatively slowly as the number of processes increases, it shows good scalability feature. The potential of our algorithm is shown by simulation study.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

We describe an algorithm for efficiently compositing partial images generated during parallel volume rendering on a distributed memory parallel computer. In this object space partitioning algorithm, each PE is assigned to several subvolumes where each subvolume has a corresponding local frame buffer. After volume rendering is performed independently for each subvolume, the partial images stored in the local frame buffers are combined to generate a complete image. During this compositing process, the communication of partial image data between the PEs is kept minimal by assigning PEs to subvolumes in an interleaved manner. This assignment makes possible a reduction in communication in the axis direction in which there is the most communication. Experimental results indicate that a 9% to 35% reduction in the total rendering time can be attained with no additional data structures and no memory overhead.

Parallelism on heterogeneous machines brings cost effectiveness, but also raises a new set of complex and challenging problems. This paper addresses the problem of estimating the minimum time taken to execute a program on a fine-grained parallel machine composed of different types of processors. In an earlier publication, we took the first step in this direction by presenting a graph-construction method which partitions a given program into several homogeneous parts and incorporates timing constraints due to heterogeneous parallelism into each part. In this paper, to make the method easier to be applied in a scheduling framework and to demonstrate its practical utility, we present an efficient implementation method and compare the results of its use to the optimal schedule lengths obtained by enumerating all possible solutions. Experimental results for several different machine models indicate that this method can be effectively used to estimate a program's minimum execution time.

Mobile databases will play an important role in mobile computing environment, to provide data storing and data retrieval functionalities which are needed by most applications. In mobile computing environment, the wireless communication poses some problems, which require us to minimize its use. Replication is a database technique that is commonly used to fulfill the requirement in minimizing network usage. In this paper, we propose two replica allocation strategies, called primary-copy tracking replica allocation (PTRA) and user majority replica allocation (UMRA), which are better suited to the mobile computing environment. Their proposals are intended to cope with cost performance issues in data replication due to user mobility in mobile computing environment. To investigate their effectiveness, we provide access cost analysis and comparison on these strategies and the static replica allocation (SRA) strategy. We show that our proposed strategies outperform the SRA strategy when user mobility (inter-cell movement) is relatively low as compared with data access rate.

This paper proposes a time-interval data model in which all temporal representation and operations can be expressed with time intervals. The model expresses not only real time intervals, in which an event exists, but also null time intervals, in which an event is suspended. We model the history of a real-world event as a composite time interval, which is defined in this paper. Operations on the composite time intervals are also defined, and it is shown how these operations can be used to express temporal constraints with time intervals.

This paper proposes a design method of feature spaces in a two-stage image recognition method that improves the recognition accuracy and efficiency in statistical image recognition. The two stages are (1) image screening and (2) image recognition. Statistical image recognition methods require a lot of calculations for spatially matching between subimages and reference patterns of the specified objects to be detected in input images. Our image screening method is effective in lowering the calculation load and improving recognition accuracy. This method selects a candidate set of subimages similar to those in the object class by using a lower dimensional feature vector, while rejecting the rest. Since a set of selected subimages is recognized by using a higher dimensional feature vector, overall recognition efficiency is improved. The classifier for recognition is designed from the selected subimages and also improves recognition accuracy, since the selected subimages are less contaminated than the originals. Even when conventional recognition methods based on linear transformation algorithms, i. e. principal component analysis (PCA) and projection pursuit (PP), are applied to the recognition stage in our method, recognition accuracy and efficiency may be improved. A new criterion, called a screening criterion, for measuring overall efficiency and accuracy of image recognition is introduced to efficiently design the feature spaces of image screening and recognition. The feature space for image screening are empirically designed subject to taking the lower number of dimensions for the feature space referred to as LS and the larger value of the screening criterion. Then, the recognition feature space which number of dimensions is referred to as LR is designed under the condition LSLR. The two detection tasks were conducted in order to examine the performance of image screening. One task is to detect the eye- and-mouth-areas in a face image and the other is to detect the text-area in a document image. The experimental results demonstrate that image screening for these two tasks improves both recognition accuracy and throughput when compared to the conventional one-stage recognition method.

In this paper, three issues concerning the linear adaptive receiver using the LMS algorithm for single-user demodulation in direct-sequence/code-division multiple-access (DS/CDMA) systems are considered. First, the convergence rate of the LMS algorithm in DS/CDMA environment is considered theoretically. Both upper and lower bounds of the eigenvalue spread of the autocorrelation matrix of receiver input signals are derived. It is cleared from the results that the convergence rate of the LMS algorithm becomes slow when the signal power of interferer is large. Second, fast converging technique using a prefilter is considered. The LMS based adaptive receiver using an adaptive prefilter adjusted by a Hebbian learning algorithm to decorrelate the input signals is proposed. Computer simulation results show that the proposed receiver provides faster convergence than the LMS based receiver. Third, the complexity reduction of the proposed receiver by prefiltering is considered. As for the reduced complexity receiver, it is shown that the performance degradation is little as compared with the full complexity receiver.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

A bicomplex representation for time-harmonic electromagnetic fields appearing in scattering and diffraction problems is given using two imaginary units i and j. Fieldsolution integral-expressions obtained in the high-frequency and low-frequency limits are shown to provide the new relation between high-frequency diffraction and low-frequency scattering. Simple examples for direct scattering problems are illustrated. It may also be possible to characterize electric or magnetic currents induced on the obstacle in terms of geometrical optics far-fields. This paper outlines some algebraic rules of bicomplex mathematics for diffraction or scattering fields and describes mathematical evidence of the solutions. Major discussions on the relationship between high-frequency and low-frequency fields are relegated to the companion paper which will be published in another journal.