To reduce the power dissipation of the receiver in accordance with the intensity of the received signal, we developed the first intra-symbol intermittent (ISI) radio-frequency (RF) front end with 0.35-µm CMOS technology. In the demodulation mechanism, the RF output of the low-noise amplifier (LNA) is down-converted to an intermediate frequency (IF) by the mixer, and the LNA and mixer operate synchronously and intermittently within the length of a single symbol. Because the time-averaged power consumption is proportional to the operating time, the demodulation can be performed with low power by making the total operating time short. We experimentally demonstrate that demodulation (BPSK: 9.6 kbps) is properly achieved with the operating-time ratio of 12%. This ISI operation of the RF front end is enabled by a newly devised fast-transition LNA and mixer. A theoretical analysis of aliasing noise reveals that RF ISI operation is more useful than current-control with continuous operation and that an operating-time ratio of 10% is optimal.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.

This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90directional coupler using the WL-CSP technology has center frequency of 25.6 GHz, insertion loss of -0.5 dB and isolation of -29.8 dB in the measurement result. The WL-CSP technology contributes to realize low-loss RF passive devices on Si CMOS chip, which is indispensable to achieve small-size, cost-effective and low-power monolithic wireless communication circuits (MWCCs).

There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.