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[Keyword] SI(16314hit)

8101-8120hit(16314hit)

  • Experimental Evaluation of Decision Criteria for WLAN Handover: Signal Strength and Frame Retransmission

    Kazuya TSUKAMOTO  Takeshi YAMAGUCHI  Shigeru KASHIHARA  Yuji OIE  

     
    PAPER-Network

      Vol:
    E90-B No:12
      Page(s):
    3579-3590

    In ubiquitous networks, Mobile Nodes (MNs) often suffer from performance degradation due to the following two reasons: (1) reduction of signal strength by the movement of an MN and intervening objects, and (2) radio interference with other WLANs. Therefore, handover initiation based on quick and reliable detection of the deterioration in a wireless link condition arising from the above two reasons is essential for achieving seamless handover. In previous studies, we focused on a handover decision criterion and described the problems related to the two existing decision criteria. Furthermore, we showed the effectiveness of the number of frame retransmissions through simulation experiments. However, a comparison of the signal strength and the number of frame retransmissions could not be examined due to the unreliability of the signal strength in simulations. Therefore, in the present paper, by employing FTP and VoIP applications, we compare the signal strength and the number of frame retransmissions as a handover decision criterion with experiments in terms of (1) and (2) in a real environment. Finally, we clarify the problem of the signal strength in contrast to the effectiveness of the number of frame retransmissions as a handover decision criterion.

  • Timing Analysis Considering Spatial Power/Ground Level Variation

    Masanori HASHIMOTO  Junji YAMAGUCHI  Hidetoshi ONODERA  

     
    PAPER-Physical Design

      Vol:
    E90-A No:12
      Page(s):
    2661-2668

    Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This paper proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load model.

  • Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis

    Yuko HARA  Hiroyuki TOMIYAMA  Shinya HONDA  Hiroaki TAKADA  Katsuya ISHII  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E90-A No:12
      Page(s):
    2853-2862

    This paper proposes a behavioral level partitioning method for efficient behavioral synthesis from a large sequential program consisting of a set of functions. Our method optimally determines functions to be inlined into the main module and the other functions to be synthesized into sub modules in such a way that the overall datapath is minimized while the complexity of individual modules is lower than a certain level. The partitioning problem is formulated as an integer programming problem. Experimental results show the effectiveness of the proposed method.

  • A Distortion-Free Learning Algorithm for Feedforward Multi-Channel Blind Source Separation

    Akihide HORITA  Kenji NAKAYAMA  Akihiro HIRANO  

     
    PAPER-Digital Signal Processing

      Vol:
    E90-A No:12
      Page(s):
    2835-2845

    FeedForward (FF-) Blind Source Separation (BSS) systems have some degree of freedom in the solution space. Therefore, signal distortion is likely to occur. First, a criterion for the signal distortion is discussed. Properties of conventional methods proposed to suppress the signal distortion are analyzed. Next, a general condition for complete separation and distortion-free is derived for multi-channel FF-BSS systems. This condition is incorporated in learning algorithms as a distortion-free constraint. Computer simulations using speech signals and stationary colored signals are performed for the conventional methods and for the new learning algorithms employing the proposed distortion-free constraint. The proposed method can well suppress signal distortion, while maintaining a high source separation performance.

  • Multiclass Boosting Algorithms for Shrinkage Estimators of Class Probability

    Takafumi KANAMORI  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E90-D No:12
      Page(s):
    2033-2042

    Our purpose is to estimate conditional probabilities of output labels in multiclass classification problems. Adaboost provides highly accurate classifiers and has potential to estimate conditional probabilities. However, the conditional probability estimated by Adaboost tends to overfit to training samples. We propose loss functions for boosting that provide shrinkage estimator. The effect of regularization is realized by shrinkage of probabilities toward the uniform distribution. Numerical experiments indicate that boosting algorithms based on proposed loss functions show significantly better results than existing boosting algorithms for estimation of conditional probabilities.

  • Joint Blind Super-Resolution and Shadow Removing

    Jianping QIAO  Ju LIU  Yen-Wei CHEN  

     
    PAPER-Image Processing and Video Processing

      Vol:
    E90-D No:12
      Page(s):
    2060-2069

    Most learning-based super-resolution methods neglect the illumination problem. In this paper we propose a novel method to combine blind single-frame super-resolution and shadow removal into a single operation. Firstly, from the pattern recognition viewpoint, blur identification is considered as a classification problem. We describe three methods which are respectively based on Vector Quantization (VQ), Hidden Markov Model (HMM) and Support Vector Machines (SVM) to identify the blur parameter of the acquisition system from the compressed/uncompressed low-resolution image. Secondly, after blur identification, a super-resolution image is reconstructed by a learning-based method. In this method, Logarithmic-wavelet transform is defined for illumination-free feature extraction. Then an initial estimation is obtained based on the assumption that small patches in low-resolution space and patches in high-resolution space share a similar local manifold structure. The unknown high-resolution image is reconstructed by projecting the intermediate result into general reconstruction constraints. The proposed method simultaneously achieves blind single-frame super-resolution and image enhancement especially shadow removal. Experimental results demonstrate the effectiveness and robustness of our method.

  • A Simple Code Allocation Algorithm Based on Asymptotic Analysis of MIMO MC-CDMA Systems in a Multi-Cell Environment

    Kyeongyeon KIM  Jaesang HAM  Chungyong LEE  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E90-B No:12
      Page(s):
    3708-3711

    Owing to frequency diversity gain and simplicity, a chip interleaved multi-carrier code division multiple access (MC-CDMA) system has been considered in a multi-cell environment, and combining it with multiple input multiple output (MIMO) schemes offers high spectral efficiency. In spite of the advantages, the system is highly affected by inter code interferences. To control them, this letter analyzes the asymptotic performance of a MIMO MC-CDMA system with a symbol level MMSE receiver in a multi-cell environment and presents an appropriate multiplexed code ratio satisfying a required error rate.

  • TCP Reassembler for Layer7-Aware Network Intrusion Detection/Prevention Systems

    Miyuki HANAOKA  Makoto SHIMAMURA  Kenji KONO  

     
    PAPER-Dependable Computing

      Vol:
    E90-D No:12
      Page(s):
    2019-2032

    Exploiting layer7 context is an effective approach to improving the accuracy of detecting malicious messages in network intrusion detection/prevention systems (NIDS/NIPSs). Layer7 context enables us to inspect message formats and the message exchanged order. Unfortunately, layer7-aware NIDS/NIPSs pose crucial implementation issues because they require full TCP and IP reassembly without losing 1) complete prevention, 2) performance, 3) application transparency, or 4) transport transparency. Complete prevention means that the NIDS/NIPS should prevent malicious messages from reaching target applications. Application transparency means not requiring any modifications to and/or reconfiguration of server and client applications. Transport transparency is not to disrupt the end-to-end semantics of TCP/IP. To the best of our knowledge, none of the existing approaches meet all of these requirements. We have developed an efficient mechanism for layer7-aware NIDS/NIPSs that does meet the above requirements. Our store-through does this by forwarding each out-of-order or IP-fragmented packet immediately after copying the packet even if it has not been checked yet by an NIDS/NIPS sensor. Although the forwarded packet might turn out to be a part of an attack message, the store-through mechanism can successfully defend against the attack by blocking one of the subsequent packets that contain another part of attack message. Testing of a prototype in Linux kernel 2.4.30 demonstrated that the overhead of our mechanism is negligible compared with that of a simple IP forwarder even with the presence of out-of-order and IP-fragmented packets. In addition, the experimental results suggest that the CPU and memory usage incurred by our store-through is not significant.

  • FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet

    Toshihiro KATASHITA  Yoshinori YAMAGUCHI  Atusi MAEDA  Kenji TODA  

     
    PAPER-Reconfigurable System and Applications

      Vol:
    E90-D No:12
      Page(s):
    1923-1931

    The present paper describes an implementation of an intrusion detection system (IDS) on an FPGA for 10 Gigabit Ethernet. The system includes an exact string matching circuit for 1,225 Snort rules on a single device. A number of studies have examined string matching circuits for IDS. However, implementing a circuit that processes a large rule set at high throughput is difficult. In a previous study, we proposed a method for generating an NFA-based string matching circuit that has expandability of processing data width and drastically reduced resource requirements. In the present paper, we implement an IDS circuit that processes 1,225 Snort rules at 10 Gbps with a single Xilinx Virtex-II Pro xc2vp-100 using the NFA-based method. The proposed circuit also provides packet filtering for an intrusion protection system (IPS). In addition, we developed a tool for automatically generating the Verilog HDL source code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit generator, the proposed system is able to update the matching rules corresponding to new intrusions and attacks. We implemented the IDS circuit on an FPGA board and evaluated its accuracy and throughput. As a result, we confirmed in a test that the circuit detects attacks perfectly at the wire speed of 10 Gigabit Ethernet.

  • High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC

    Chun-Lung HSU  Mean-Hom HO  

     
    PAPER-System Level Design

      Vol:
    E90-A No:12
      Page(s):
    2818-2825

    This paper proposes a flexible VLSI architecture design for motion estimation in H.264/AVC using a high-efficiency variable block-size decision (VBSD) approach. The proposed VBSD approach can perform a full motion search on integrating the 44 block sizes into 48, 84, 88, 816, 168, or 1616 block sizes and then appropriately select the optimal modes for motion compensation operating. In other words, the proposed architecture based on the VBSD approach can effectively reduce the encoding time of the motion estimation by dealing with different block sizes under 1616 searching range. Using the TSMC 0.18-µm CMOS technology, the proposed architecture has been successfully realized. Simulation and verification results show that the proposed architecture has significant bit-rate reduction and small PSNR degradation. Also, the physical chip design revealed that the maximum frame rate of this work can process 704 fps with QCIF (176144), 176 fps with CIF (352288) and 44 fps with 4CIF (704576) video resolutions under lower gate counts and higher working frequency.

  • Risk-Sensitive Learning via Minimization of Empirical Conditional Value-at-Risk

    Hisashi KASHIMA  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E90-D No:12
      Page(s):
    2043-2052

    We extend the framework of cost-sensitive classification to mitigate risks of huge costs occurring with low probabilities, and propose an algorithm that achieves this goal. Instead of minimizing the expected cost commonly used in cost-sensitive learning, our algorithm minimizes conditional value-at-risk, also known as expected shortfall, which is considered a good risk metric in the area of financial engineering. The proposed algorithm is a general meta-learning algorithm that can exploit existing example-dependent cost-sensitive learning algorithms, and is capable of dealing with not only alternative actions in ordinary classification tasks, but also allocative actions in resource-allocation type tasks. Experiments on tasks with example-dependent costs show promising results.

  • Coverage Enhancement in TDD-OFDMA Downlink by Using Simple-Relays with Resource Allocation and Throughput Guarantee Scheduler

    Young Min KI  Dae Wook BYUN  Dong Ku KIM  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E90-B No:12
      Page(s):
    3704-3707

    Simple-relay aided resource allocation (SRARA) schemes are incorporated with throughput guarantee scheduling (TGS) in IEEE 802.16 type time division duplex--orthogonal frequency division multiple access (TDD-OFDMA) downlink in order to enhance service coverage, where the amount of resources at each relay is limited due to either its available power which is much smaller than base station (BS) power or the required overhead. The performance of SRARA schemes is evaluated with both proportional fair (PF) and TGS schedulers at 64 kbps and 128 kbps user throughput requirements when total RS power is set to 500 mW or 1 W. For SRARA with RSs of relatively lower power (500 mW), schemes that put total power into only one subchannel offer larger coverage than when both subchnnels are used with equal power allocation, while the RS with evenly power-allocated two subchannels could provide larger coverage gain for a relatively higher power (1 W). Depending upon the target throughputs it is shown which of the relay scheme or scheduler design would play more important role in improving coverage. In a lower target (64 kbps), more improvement comes from relay scheme rather than scheduler design. For a relatively higher level (128 kbps), it comes from scheduler design rather than relay due to the fact that simple relay can't help using strictly limited amount of resources.

  • A Protocol for Policy-Based Session Control in Disruption Tolerant Sensor Networks

    Ryohei SUZUKI  Kaoru SEZAKI  Yoshito TOBE  

     
    PAPER

      Vol:
    E90-B No:12
      Page(s):
    3426-3433

    Recently there has been a great deal of research on using mobility in sensor networks to assist their sensing tasks. In this paper, we propose a policy-based session control protocol for Multi-Robot Sensor Networks (MRSNs) called Billiards. In a MRSN, all messages are transported by the physical motion of participants (mobile nodes) in the network. When a large volume of data or continuous data is required to be transferred, there exists a problem determining how the data is fragmented and how the mobile nodes are formed for carrying the data to the destination. To overcome the issues, we propose a suitable method of session control which is determined based on a state of surrounding mobile nodes such as number, maximum-velocity and buffer-size. Billiards also takes a system policy of delay minimization into consideration. In this paper, we describe the protocol and model of Billiards and analyze the model. We evaluated the performance of Billiards utilizing mobile robots which are equipped with MICA2 mote and comparing with non optimized method. The experimental results demonstrate that Billiards achieves less delay than non optimized method at every velocity and buffer-size of each robot.

  • Resource Allocations for TDD OFDMA Cellular Systems Considering Traffic Asymmetries

    Seungyoung PARK  Yeonwoo LEE  Sangboh YUN  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E90-B No:12
      Page(s):
    3691-3694

    The time division duplex cellular system can support various downlink and uplink traffic ratios by setting the downlink and uplink transmission periods appropriately. However, it causes severe co-channel interference problem when some cells are active in the downlink while the others are in the uplink [2]. To mitigate this problem, a resource allocation scheme combined with sectorization is proposed for orthogonal frequency division multiple access. Simulations demonstrate that the proposed scheme improves both spectral efficiency and outage performance compared to the conventional allocation schemes.

  • Lifetime Prediction Routing Protocol for Wireless Sensor Networks

    Minho SEO  Wonik CHOI  Yoo-Sung KIM  Jaehyun PARK  

     
    LETTER-Network

      Vol:
    E90-B No:12
      Page(s):
    3680-3681

    We propose LPDD (Lifetime Prediction Directed Diffusion), a novel energy-aware routing protocol for sensor networks that aims at increasing network survivability without a significant increase in latency. The key concept behind the protocol is the adaptive selection of routes by predicting the battery lifetime of the minimum energy nodes along the routes.

  • Adaptive Guard Symbol Insertion Method for One-Cell Reuse TDMA Cellular Systems

    Seiichiro HORIKAWA  Osamu MUTA  Yoshihiko AKAIWA  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E90-B No:12
      Page(s):
    3724-3728

    In this paper, we propose an adaptive guard symbol insertion method for one-cell reuse TDMA cellular systems in which co-channel interference is reduced by adaptively selecting the best transmit-pulse waveform with different guard (null-) symbols according to the average error power (AEP) corresponding to signal-to-interference and noise power ratio (SINR), even though the same frequency channel is used at all base stations. Using the proposed system, current TDMA-based systems are readily extensible to one-cell reuse systems, which achieves higher spectrum efficiency. The system capacity is enhanced using the proposed method; moreover, the required qualities such as blocking probability and outage probability are retained.

  • NRD-Guide Passive Components and Devices for Millimeter Wave Wireless Applications

    Tsukasa YONEYAMA  Hirokazu SAWADA  Takashi SHIMIZU  

     
    INVITED PAPER

      Vol:
    E90-C No:12
      Page(s):
    2170-2177

    Owing to simple structure, low cost and high performance, NRD-guide millimeter wave circuits have attracted much attention in recent years. In this paper, a variety of NRD-guide passive components are reviewed with emphasis on design techniques and performance estimation in the 60 GHz frequency band where the license-free advantage is available. The passive components to be discussed here include compact bends, wideband hybrid couplers, practical three-port junctions, versatile E-plane filters, and effective feeding structures for lens antennas. Some of them are employed to construct millimeter wave transceivers. Eye patterns observed at 1.5 Gbps confirm the potential ability of the fabricated NRD-guide transceivers for high bit-rate, wireless applications.

  • Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines

    Hiroshi KAWAGUCHI  Danardono Dwi ANTONO  Takayasu SAKURAI  

     
    PAPER-Physical Design

      Vol:
    E90-A No:12
      Page(s):
    2669-2681

    Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied; a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%.

  • An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults

    Jin-Fu LI  Chao-Da HUANG  

     
    PAPER-Memory Design and Test

      Vol:
    E90-A No:12
      Page(s):
    2703-2711

    This paper presents an efficient diagnosis scheme for RAMs. Three March-based algorithms are proposed to diagnose simple functional faults of RAMs. A March-15N algorithm is used for locating and partially diagnosing faults of bit-oriented or word-oriented memories, where N represents the address number. Then a 3N March-like algorithm is used for locating the aggressor words (bits) of coupling faults (CFs) in word-oriented (bit-oriented) memories. It also can distinguish the faults which cannot be identified by the March-15N algorithm. Thus, the proposed diagnosis scheme can achieve full diagnosis and locate aggressors with (15N + 3mN) Read/Write operations for a bit-oriented RAM with m CFs. For word-oriented RAMs, a March-like algorithm is also proposed to locate the aggressor bit in the aggressor word with 4 log2B Read/Write operations, where B is the word width. Analysis results show that the proposed diagnosis scheme has higher diagnostic resolution and lower time complexity than the previous fault location and fault diagnosis approaches. A programmable built-in self-diagnosis (BISD) design is also implemented to perform the proposed diagnosis algorithms. Experimental results show that the area overhead of the BISD is small--only about 2.17% and 0.42% for 16 K8-bit and 16 K128-bit SRAMs, respectively.

  • State Machines as Inductive Types

    Kazuhiro OGATA  Kokichi FUTATSUGI  

     
    LETTER-Concurrent Systems

      Vol:
    E90-A No:12
      Page(s):
    2985-2988

    We describe a way to write state machines inductively. The proposed method makes it possible to use the standard techniques for proving theorems on inductive types to verify that state machines satisfy invariant properties. A mutual exclusion protocol using a queue is used to exemplify the proposed method.

8101-8120hit(16314hit)