In this paper, we describe a single system image (SSI) architecture for distributed systems. The SSI architecture is constructed through three components: single process space (SPS), process migration, and dynamic load balancing. These components attempt to share all available resources in the cluster among all executing processes, so that the distributed system operates like a single node with much more computing power. To this end, we first resolve broken pipe problems and bind errors on server socket in process migration. Second, we realize SPS based on block process identifier (PID) allocation. Finally, we design and implement a dynamic load balancing scheme. The dynamic load balancing scheme exploits our novel metric, effective tasks, to effectively distribute jobs to a large distributed system. The experimental results show that these three components present scalability, new functionality, and performance improvement in distributed systems.

Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 710-µm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.

This paper discusses design of Generalized Predictive Control (GPC) scheme. GPC is designed in two cases; the first is a dual-rate (DR) system, where the sampling interval of a plant output is an integer multiple of the holding interval of a control input, and the second is a fast-rate single-rate (FR-SR) system, where both the holding and sampling intervals are equal to the holding interval of the DR system. Furthermore, the relation between them is investigated, and this study gives the conditions that FR-SR and DR GPC become equivalent. To this end, a future reference trajectory of DR GPC is rewritten, and a future predictive output of the FR-SR GPC is rearranged.

In this paper, a novel decentralized adaptive neural network controller is proposed for a class of large-scale nonlinear systems with unknown nonlinear, nonaffine subsystems and unknown nonlinear interconnections. The stability of the closed loop system is guaranteed by introducing a robust adaptive bound based on Lyapunov stability analysis. A radial-basis function type neural network is used in the paper. To show the effectiveness of the proposed method, we performed some simulation studies. The results of simulation become very promising.

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.

This paper presents media processor architectures for automotive applications. Media processing applications with their requirements for LSI implementations are first described for vision based driver assistance as well as graphical user interface for car navigation using 3D graphics. Then, parallel processing architectures for vision and graphics in these applications are reviewed with their performance and cost. After that, future trends of automotive media processing such as integration of vision and 3D graphics functions are shown with their applications and the required performance. Moreover, parallel processing architectures are discussed for the integration of vision and graphics. Finally, an prospect of a next-generation media processing LSI for automotives is provided.

The security notion of indifferentiability was proposed by Maurer, Renner, and Holenstein in 2004. In 2005, Coron, Dodis, Malinaud, and Puniya discussed the indifferentiability of hash functions. They have shown that the Merkle-Damgård construction is not secure in the sense of indifferentiability. In this paper, we analyze the security of single-block-length and rate-1 compression functions in the sense of indifferentiability. We formally show that all single-block-length and rate-1 compression functions, which include the Davies-Meyer compression function, are insecure. Furthermore, we show how to construct a secure single-block-length and rate-1 compression function in the sense of indifferentiability. This does not contradict our result above.

Broadcast and synchronization techniques are used for cache coherence control in conventional larger scale snoop-based SMP systems. The penalty for synchronization is directly proportional to system size. Meanwhile, advances in LSI technology now enable placing a memory controller on a CPU die. The latency to access directly linked memory is drastically reduced by an on-die controller. Developing an enterprise server system with these CPUs allows us an opportunity to achieve higher performance. Though the penalty of synchronization is counted whenever a cache miss occurs, it is necessary to improve the coherence method to receive the full benefit of this effect. In this paper, we demonstrate a coherence directory organization that fits into DSM enterprise server systems. Originally, a directory-based method was adopted in high performance computing systems because of its huge scalability in comparison with snoop-based method. Though directory capacity miss and long directory access latency are the major problems of this method, the relaxed scalability requirement of enterprise servers is advantageous to us to solve these problems along with an advanced LSI technology. Our proposed directory solves both problems by implementing a full bit vector level map of the coherence directory on an LSI chip. Our experimental results validate that a system controlled by our proposed directory can surpass a snoop-based system in performance even without applying data localization optimization to an online transaction processing (OLTP) workload.

Accompanying with the rapid popularization of portable equipments, it becomes very important to make the battery lifetime longer without increasing the battery size. Especially toward the ubiquitous computing age, long battery lifetime in a tight size limitation will be highly demanded. It will be invaluable for intelligent sensor for cars and robots, too. This paper proposes an algorithm to optimize the battery lifetime in the restriction of total size, by simultaneous analysis of operation condition of battery, buck converter, and LSI. We discuss accurate design models of those components at the same time.

We show the equivalence between the conventional frame synchronization in single-carrier systems and integer part estimation of frequency offset in OFDM systems and propose an efficient synchronization scheme. The proposed scheme achieves both OFDM symbol/frame timing and frequency offset estimation with only one well-designed OFDM training symbol, while previous synchronization algorithms need two OFDM training symbols at least. Numerical analysis shows that the proposed frequency estimator nearly achieves the Cramér-Rao lower bound for the variance of the frequency offset estimate, despite the reduction in the training sequence length.

Machine learning techniques have long been applied in many fields and have gained a lot of success. The purpose of learning processes is generally to obtain a set of parameters based on a given data set by minimizing a certain objective function which can explain the data set in a maximum likelihood or minimum estimation error sense. However, most of the learned parameters are highly data dependent and rarely reflect the true physical mechanism that is involved in the observation data. In order to obtain the inherent knowledge involved in the observed data, it is necessary to combine physical models with learning process rather than only fitting the observations with a black box model. To reveal underlying properties of human speech production, we proposed a learning process based on a physiological articulatory model and a coarticulation model, where both of the models are derived from human mechanisms. A two-layer learning framework was designed to learn the parameters concerned with physiological level using the physiological articulatory model and the parameters in the motor planning level using the coarticulation model. The learning process was carried out on an articulatory database of human speech production. The learned parameters were evaluated by numerical experiments and listening tests. The phonetic targets obtained in the planning stage provided an evidence for understanding the virtual targets of human speech production. As a result, the model based learning process reveals the inherent mechanism of the human speech via the learned parameters with certain physical meaning.

A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results.

Dividing a lecture speech into segments and providing those segments as learning objects are quite general and convenient way to construct e-learning resources. However it is difficult to assign an appropriate title to each object that reflects its content. Since there are various aspects of analyzing discourse segments, it is inevitable that researchers will face the diversity when describing the "meanings" of discourse segments. In this paper, we propose the assignment of discourse segment titles from the representation of their "meanings." In this assigning procedure, we focus on the speaker's evaluation for the event or the speech object. To verify the effectiveness of our idea, we examined identification of the segment boundaries from the titles that were described in our procedure. We confirmed that the result of the identification was more accurate than that of intuitive identification.

Inter-Vehicle Communication (IVC) is one of the most important technologies to realize advanced Intelligent Transport Systems (ITS). We extensively apply the IVC technology to the communications between pedestrians and vehicles. We call this kind of communications VPEC (Vehicle-PEdestrian Communications). The objective of this paper is to present an effective control scheme for VPEC and to evaluate the performance of proposed scheme by experiments. We deal with direct communications between pedestrians and vehicles. Due to the battery shortage of pedestrians' terminals (p-node), we have presented a reflect-transmission scheme. In this paper, we propose a new access protocol for reflect-transmission scheme, and show its validity by various experiments with several vehicles.

A new scheme for reducing optical beat interference noise in a reflective semiconductor optical amplifier based wavelength division multiplexed/subcarrier multiplexing -- passive optical network is proposed. This method uses an Fabry Perot laser locked by modulated lights from optical network units in a central office. As an experimental verification, it is reported that carrier to noise ratio is enhanced by 10 dB and power penalty is improved by 16 dB.

For the closed loop multiple-input-multiple-output (MIMO) systems, Fisher's adaptive bit loading algorithm gives the best error performance by jointly optimizing the transmit powers, rates, and number of streams. However, its good performance comes at the cost of high and variable computational complexity for the joint optimization. In this letter, we propose an efficient multi-mode precoding algorithm using a simplified mode table. Numerical results show that the proposed algorithm provides almost the same performance as Fischer's with much less computational complexity.

In this paper, we present a method to automatically acquire a large-scale vocabulary of evaluative expressions from a large corpus of blogs. For the purpose, this paper presents a semi-supervised method for classifying evaluative expressions, that is, tuples of subjects, their attributes, and evaluative words, that indicate either favorable or unfavorable opinions towards a specific subject. Due to its characteristics, our semi-supervised method can classify evaluative expressions in a corpus by their polarities, starting from a very small set of seed training examples and using contextual information in the sentences the expressions belong to. Our experimental results with real Weblog data as our corpus show that this bootstrapping approach can improve the accuracy of methods for classifying favorable and unfavorable opinions. We also show that a reasonable amount of evaluative expressions can be really acquired.

Several approaches have been studied to cope with the exceptional features of non-segmented languages. When there is no explicit information about the boundary of a word, segmenting an input text is a formidable task in language processing. Not only the contemporary word list, but also usages of the words have to be maintained to cover the use in the current texts. The accuracy and efficiency in higher processing do heavily rely on this word boundary identification task. In this paper, we introduce some statistical based approaches to tackle the problem due to the ambiguity in word segmentation. The word boundary identification problem is then defined as a part of others for performing the unified language processing in total. To exhibit the ability in conducting the unified language processing, we selectively study the tasks of language identification, word extraction, and dictionary-less search engine.

This paper presents a method to automatically acquire a given noun's telic and agentive roles from corpus data. These relations form part of the qualia structure assumed in the generative lexicon, where the telic role represents a typical purpose of the entity and the agentive role represents the origin of the entity. Our proposed method employs a supervised machine-learning technique which makes use of template-based contextual features derived from token instances of each noun. The output of our method is a ranked list of verbs for each noun, across the different qualia roles. We also propose a variant of Spearman's rank correlation to evaluate the correlation of two top-N ranked lists. Using this correlation method, we represent the ability of the proposed method to identify qualia structure relative to a conventional template-based method.

This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.