An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.

Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).

We have proposed and successfully demonstrated a two step method for localizing defects on an LSI chip. The first step is the same as a conventional laser-SQUID (L-SQUID) imaging where a SQUID and a laser beam are fixed during LSI chip scanning. The second step is a new L-SQUID imaging where a laser beam is stayed at the point, located in the first step results, during SQUID scanning. In the second step, a SQUID size (Aeff) and the distance between the SQUID and the LSI chip (ΔZ) are key factors limiting spatial resolution. In order to improve the spatial resolution, we have developed a micro-SQUID and the vacuum chamber housing both the micro-SQUID and the LSI chip. The Aeff of the micro-SQUID is a thousand of that of a conventional SQUID. The minimum value of ΔZ was successfully reduced to 25 µm by setting both the micro-SQUID and an LSI chip in the same vacuum chamber. The spatial resolution in the second step was shown to be 53 µm. Demonstration of actual complicated defects localization was succeeded, and this result suggests that the two step localization method is useful for LSI failure analysis.

We have improved the optical beam induced resistance change (OBIRCH) system so as to detect (1) a current path as small as 10-50 µA from the rear side of a chip, (2) current paths in silicide lines as narrow as 0. 2 µm, (3) high-resistance Ti-depleted polysilicon regions in 0. 2 µm wide silicide lines, and (4) high-resistance amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm 5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.

Solder joint reliability was studied for hybrid ICs, in which chip components such as FETs, resistors and capacitors were mounted with Sn-Sb solder on an insulated Al substrate and transfer-molded with epoxy resin. Suitable resin selection for molding was also studied. The structure was estimated to have a lifetime of more than ten thousand cycles in the thermal cycling test under the condition of -55/150, for FETs and passive elements. Equivalent plastic strains generated in the soldering layer for the non-molded structure were 4. 6% for the FETs and 3.5% for the passive elements. But, these strains were approximately 1/3 to 1/2 and 1/10 for the molded structure, respectively. This was the main reason for high reliability of the molded structure. Resins with a wide range of thermal expansion coefficient(8-26 ppm/)could be put to practical use, because of the higher reliability of the molded structure. However, a thermal expansion coefficient of about 15 ppm/ was prefered to decrease stress at the interface between the substrate and the molding resin.