We propose a stability-guaranteed horizon size (SgHS) for stabilizing receding horizon control (RHC). It is shown that the proposed SgHS can be represented explicitly in terms of the known parameters of the given system model and is independent of the terminal weighting matrix in the cost function. The proposed SgHS is validated via a numerical example.

One of the system greatly affecting the performance of a database server is the size-division of buffer pools. This letter proposes an adaptive control method of the buffer pool sizes. This method obtains the nearly optimal division using only observed response times in a comparatively short duration.

Providing data availability in a high performance computing environment is very important, especially in this data-intensive world. Most clusters either equip with RAID (Redundant Array of Independent Disks) devices or use redundant nodes to protect data from loss. However, neither of these can really solve the reliability problem incurred in a striped file system. Striping provides an efficient way to increase I/O throughput both in the distributed and parallel paradigms. But it also reduces the overall reliability of a disk system by N fold, where N is the number of independent disks in the system. Parallel Virtual File System (PVFS) is an open source parallel file system which has been widely used in the Linux environment. Its striping structure is good for performance but provides no fault tolerance. We implement Reliable Parallel File System (RPFS) based on PVFS but with reliability support. Our quantitative analysis shows that MTTF (Mean Time To Failure) of our RPFS is better than that of PVFS. Besides, we propose a parity cache table (PCT) to alleviate the penalty of parity updating. The evaluation of our RPFS shows that its read performance is almost the same as that of PVFS (2% to 13% degradation). As to the write performance, 28% to 45% improvement can be achieved depending on the behavior of the operations.

In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology enables fast parallel search of the code word table. At the same time, the code word table is optimized according to the frequency of received input symbols and is up-dated in real-time. Since these two functions work in parallel, the proposed architecture realizes fast parallel encoding and keeps a constantly high compression ratio. Evaluation results for the JPEG application show that the proposed architecture can achieve up to 28% smaller encoded picture sizes than the conventional architectures. The obtained encoding time can be reduced by 95% in comparison to a conventional SRAM-based architecture, which is suitable even for the latest end-user-devices requiring fast frame-rates. Furthermore, the proposed architecture provides the only encoder that can simultaneously realize small compressed data size and fast processing speed.

This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective table-lookup-coding solutions. The multi-ported CAM adopts a Flexible Multi-ported Content Addressable Memory (FMCAM) technology, which represents an effective parallel processing architecture and was previously reported in [1]. To achieve a high-speed parallel table-lookup-coding solution, FMCAM is improved by additional schemes for a single search mode and counting value setting mode, so that it permits fast parallel table-lookup-coding operations. Evaluation results for Huffman encoding within the JPEG application show that a synthesized semi-custom ASIC implementation of the proposed architecture can already reduce the required clock-cycle number by 93% in comparison to a conventional DSP. Furthermore, the performance per area unit, measured in MOPS/mm2, can be improved by a factor of 3.8 in comparison to parallel operated DSPs. Consequently, the proposed architecture is very suitable for FPGA/ASIC implementation, and is a promising solution for small area integrated realization of real-time table-lookup-coding applications.

A tri-template-based codes (TTBC) method is proposed to reduce test cost of intellectual property (IP) cores. In order to reduce test data volume (TDV), the approach utilizes three templates, i.e., all 0, all 1, and the previously applied test data, for generating the subsequent test data by flipping the inconsistent bits. The approach employs a small number of test channels I to supply a large number of internal scan chains 2I-3 such that it can achieve significant reduction in test application time (TAT). Furthermore, as a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is suitable for IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT and the given test set. Theoretical analysis and experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.

The UWB (ultra-wideband) pulse radar is a promising candidate as an environment measurement method for rescue robots. Radar imaging to locate a nearby target is known as an ill-posed inverse problem, on which various studies have been done. However, conventional algorithms require long computational time, which makes it difficult to apply them to real-time operations of robots. We have proposed a fast radar imaging algorithm, the SEABED algorithm, for UWB pulse radars. This algorithm is based on a reversible transform, BST (Boundary Scattering Transform), between the target shape and the observed data. This transform enables us to estimate target shapes quickly and accurately in a noiseless environment. However, in a noisy environment the image estimated by the SEABED algorithm is degraded because BST utilizes differential operations. We have also proposed an image stabilization method, which utilizes the upper bound of the smoothness of received data. This method can be applied only to convex objects, not to concave ones. In this paper, we propose a fractional BST, which is obtained by expanding the conventional BST, and an image stabilization method by using the fractional BST. We show that the estimated image can be stabilized regardless of the shape of target.

Data retrieval is used to obtain a particular data item from a database. A user requests an item in the database from a database server by sending a query, and obtains the item from an answer to the query. Security requirements of data retrieval include protecting the privacy of the user, the secrecy of the database, and the consistency of answers. In this paper, a data retrieval scheme which satisfies all the security requirements is defined and an efficient construction is proposed. In the proposed construction, the size of a query and an answer is O((log N)2), and the size of data published by the database server when the database is updated is only O(1). The proposed construction uses the Merkle tree, a commitment scheme, and Oblivious Transfer. The proof of the security is given under the assumption that the used cryptographic schemes are secure.

We give the necessary and sufficient conditions for a one-dimensional discrete-time autonomous binary cellular neural networks to be stable in the case of fixed boundary. The results are complete generalization of our previous one [16] in which the symmetrical connections were assumed. The conditions are compared with some stability conditions so far known.

This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

Stability analysis is one of the most important problems in analysis of hybrid dynamical systems. In this paper, a computational method of Lyapunov functions is proposed for stability analysis of hybrid automata that have set-valued vector fields. For this purpose, a formulation of matrix-valued sums of squares is provided and applied to derive an LMI/LME problem whose solution yields a Lyapunov function.

Secret sharing is a method for distributing a secret among a party of participants. Each of them is allocated a share of the secret, and the secret can only be reconstructed when the shares are combined together. We have been proposing a secret sharing distributed database system (SSDDB) that uses a secret sharing scheme to improve confidentiality and robustness of distributed database systems. This paper proposes a vertical partitioning algorithm for the SSDDB, and evaluates the algorithm by computational experiments.

Combined input-crosspoint buffered (CICB) packet switches have been of research interest in the last few years because of their high performance. These switches provide higher performance than input-buffered (IB) packet switches while requiring the crosspoint buffers run at the same speed as that of the input buffers in IB switches. Recently, it has been shown that CICB switches with one-cell crosspoint buffers, virtual output queues, and simple input and output arbitrations, provide 100% throughput under uniform traffic. However, it is of general interest to know the maximum throughput that a CICB switch, with no speedup, can provide under admissible traffic. This paper analyzes the throughput performance of a CICB switch beyond uniform traffic patterns and shows that a CICB switch with one-cell crosspoint buffers can provide 100% throughput under admissible traffic while using no speedup.

Most commercial Web sites dynamically generate their contents through a three-tier server architecture composed of a Web server, an application server, and a database server. In such an architecture, the database server easily becomes a bottleneck to the overall performance. In this paper, we propose WDBAccel, a high-performance database server accelerator that significantly improves the throughput of database processing. WDBAccel eliminates costly, complex query processing needed to obtain query results by reusing the results from previous queries for subsequent queries. This differentiates WDBAccel from other database cache systems, which employ traditional query processing. WDBAccel further improves its performance by fully utilizing main memory as the primary storage. This paper presents the design and implementation of the WDBAccel as well as the results of performance evaluation with a prototype.

The output limits of the power system stabilizer (PSS) can improve the system damping performance immediately following a large disturbance. Due to non-smooth nonlinearities from the saturation limits, these values cannot be determined by the conventional tuning methods based on linear analysis. Only ad hoc tuning procedures have been used. A nonlinear least squares method, which is the Gauss-Newton optimization algorithm, is used in this paper. The gradient required in the Gauss-Newton method can be computed by applying trajectory sensitivities from the hybrid system model with the differential-algebraic-impulsive-switched (DAIS) structure. The optimal output limits of the PSS tuned by the proposed method are evaluated by time-domain simulation in a multi-machine power system (MMPS).

In this paper, the interpolation line search (ILS) algorithm to find the desirable step length in a numerical optimization method is investigated to determine the optimal saturation limits with non-smooth nonlinearities. The simple steepest descent algorithm is used to illustrate that the ILS algorithm can provide adequate reductions in an objective function at minimal cost with fast convergence. The power system stabilizer (PSS) with output limits is used as an example for a nonlinear controller to be tuned. The efficient computation to implement the ILS algorithm in the steepest descent method is available by using the hybrid system model with the differential-algebraic-impulsive-switched (DAIS) structure. The simulation results are given to show the performance improved by the ILS algorithm.

This paper introduces a common database, an evaluation framework, and its baseline recognition results for in-car speech recognition, CENSREC-3, as an outcome of the IPSJ-SIG SLP Noisy Speech Recognition Evaluation Working Group. CENSREC-3, which is a sequel to AURORA-2J, has been designed as the evaluation framework of isolated word recognition in real car-driving environments. Speech data were collected using two microphones, a close-talking microphone and a hands-free microphone, under 16 carefully controlled driving conditions, i.e., combinations of three car speeds and six car conditions. CENSREC-3 provides six evaluation environments designed using speech data collected in these conditions.

This paper proposes a new codec design method based on JPEG for face images and presents its application to face recognition. Quantization table is designed using the R-D optimization for the Yale face database. In order to use in the embedded systems, fast codec design is also considered. The proposed codec achieves better compression rates than JPEG codec for face images. In face recognition experiments using the linear discriminant analysis (LDA), the proposed codec shows better performance than JPEG codec.

We give necessary and sufficient conditions for a 1-D DBCNN (1-dimensional discrete-time binary cellular neural network) with an external input to be stable in terms of connection coefficients. The results are generalization of our previous one [18],[19] in which the input was assumed to be zero.