This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

This paper presents a wavelength lock system using a Z-cut quartz etalon supported at the middle point. The Z-cut quartz etalon possesses the cavity length modulation and the low temperature coefficient. We propose a Z-cut quartz etalon supported at the middle point in order to improve the modulation index and response time. The mechanism of the center supported Z-cut quartz etalon is described. We also show that the etalon possesses a high modulation index, a high Q factor, and a rapid response time in experimental results. A self-tuning dither oscillator realized by using quartz etalon is also described.

In 2002, Zhu et al. proposed a password authenticated key exchange protocol based on RSA such that it is efficient enough to be implemented on most of the target low-power devices such as smart cards and low-power Personal Digital Assistants in imbalanced wireless networks. Recently, YEH et al. claimed that Zhu et al.'s protocol not only is insecure against undetectable on-line password guessing attack but also does not achieve explicit key authentication. Thus they presented an improved version. Unfortunately, we find that YEH et al.'s password guessing attack does not come into existence, and that their improved protocol is vulnerable to off-line dictionary attacks. In this paper we describe our observation in details, and also comment for the original protocol on how to achieve explicit key authentication as well as resist against other existent attacks.

In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no-addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.

A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not probabilistic. Experiments on the ISCAS benchmark circuits show that the average diagnosis resolution is less than ten scan cells.

In this letter, we introduce the concept of k-error lattice structure to describe the stability of lattice structure for pseudorandom number sequences, give some of its properties, and make a study of the relationship between the k-error lattice structure and the k-error linear complexity. These properties and the relationship create an elementary framework to study the stability of the lattice structure of pseudorandom number sequences.

We report tunable optical devices based on fiber Bragg gratings (FBGs), whose filtering characteristics are controlled by strain distributions. These devices include a widely wavelength tunable filter, a tunable group-velocity dispersion (GVD) compensator, a tunable dispersion slope (DS) compensator, and a variable-bandwidth optical add/drop multiplexer (OADM), which will play important roles for next-generation reconfigurable optical networks.

This research aims to construct a high-quality Japanese TTS (Text-to-Speech) system that has high flexibility in treating prosody. Many TTS systems have implemented a prosody control system but such systems have been fundamentally designed to output speech with a standard pitch and speech rate. In this study, we employ a unit selection-concatenation method and also introduce an analysis-synthesis process to provide precisely controlled prosody in output speech. Speech quality degrades in proportion to the amount of prosody modification, therefore a target cost for prosody is set to evaluate prosodic difference between target prosody and speech candidates in such a unit selection system. However, the conventional cost ignores the original prosody of speech segments, although it is assumed that the quality deterioration tendency varies in relation to the pitch or speech rate of original speech. In this paper, we propose a novel cost function design based on the prosody of speech segments. First, we recorded nine databases of Japanese speech with different prosodic characteristics. Then with respect to the speech databases, we investigated the relationships between the amount of prosody modification and the perceptual degradation. The results indicate that the tendency of perceptual degradation differs according to the prosodic features of the original speech. On the basis of these results, we propose a new cost function design, which changes a cost function according to the prosody of a speech database. Results of preference testing of synthetic speech show that the proposed cost functions generate speech of higher quality than the conventional method.

Authenticated Key Establishment (AKE) protocols enable two entities, say a client (or a user) and a server, to share common session keys in an authentic way. In this paper, we review the previous AKE protocols, all of which turn out to be insecure, under the following realistic assumptions: (1) High-entropy secrets that should be stored on devices may leak out due to accidents such as bugs or mis-configureations of the system; (2) The size of human-memorable secret, i.e. password, is short enough to memorize, but large enough to avoid on-line exhaustive search; (3) TRM (Tamper-Resistant Modules) used to store secrets are not perfectly free from bugs and mis-configurations; (4) A client remembers only one password, even if he/she communicates with several different servers. Then, we propose a simple leakage-resilient AKE protocol (cf.[41]) which is described as follows: the client keeps one password in mind and stores one secret value on devices, both of which are used to establish an authenticated session key with the server. The advantages of leakage-resilient AKEs to the previous AKEs are that the former is secure against active adversaries under the above-mentioned assumptions and has immunity to the leakage of stored secrets from a client and a server (or servers), respectively. In addition, the advantage of the proposed protocol to is the reduction of memory size of the client's secrets. And we extend our protocol to be possible for updating secret values registered in server(s) or password remembered by a client. Some applications and the formal security proof in the standard model of our protocol are also provided.

In this letter, we provide a solution to the stabilization problem of a class of Lipschitz nonlinear systems by output feedback. Via the newly proposed nonlinearity characterization function (NCF) concept, we propose an effective method in designing an output feedback controller. Under the suggested sufficient condition which is derived by using the NCF, the proposed control scheme achieves the global exponential stabilization.

Building next generation routers with the capability of forwarding multiple millions of packets per second is required for the increasing demand for high bandwidth on the Internet. Reducing the required memory size of the forwarding table is a possible solution since small forwarding table can be integrated into the application specific integrated circuit (ASIC). In this paper a hash technique is developed to reduce the size of the IP forwarding table. The proposed data structure is a compressed 8-8-8-8 multibit trie that is based on hash tables of 4-bit addresses. Two optimization techniques are also proposed to further improve the performance of the proposed schemes. Our experimental results show that the proposed hashing-based schemes are better than the Small Forwarding Table scheme both in memory size and lookup latency.

A switched nonlinear system is considered, and the interval between two consecutive switchings is assumed to be greater than a value called "the dwell time." When switching among nonlinear systems, using a constant dwell time generally fails to lead to stability. In this letter, a state dependent dwell time function with convergence guarantees is presented for discrete-time stable nonlinear systems.

Many P2P lookup services based on distributed hash tables (DHT) have appeared recently. These schemes are built upon overlay networks and ignore distance to the target resources. As a result, P2P lookups often suffer from unnecessarily long routes in the underlay network, which we call overlay dilation. This paper proposes a new scheme for resource routing, called hybrid hierarchical overlay routing, dubbed Hyho. We introduce distance-weighted Bloom filters (dwBFs) as a concise representation of routing information for scattered resources in overlay networks. To further reduce the size of Bloom filters, so that they are linear in the number of distinct resources, Hyho splits overlay networks in accordance with DHT, where each subnetwork has a smaller set of resources and spans the entire network thinly. As a result, Hyho constructs a hierarchical overlay network and routes requests accordingly. Simulation results show that Hyho can reduce overlay dilation to one half that yielded by the Chord lookup service.

In this paper, usage of undefined states on a State Transition Graph (STG) is addressed to obtain high fault coverage, in the area of Synthesis For Testability (SFT) of synchronous sequential circuits. Basically, a given STG could be modified by adding undefined states and distinguishable transitions so that each state might be included in one strongly-connected component as much as possible. Such modification decreases the number of redundant faults caused by the existence of unreachable states on an STG. For the modification, we propose two algorithms for both incompletely-specified STGs and completely-specified STGs, respectively. In case of incompletely-specified STGs, undefined states are added using unspecified transitions of defined states. In case of completely-specified STGs, undefined states are added by changing transitions specified on an STG while preserving state equivalence. Experimental results with MCNC benchmarks show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, resulting in high fault coverage as well as short test generation time

In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3-input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 µm CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.

This paper presents optimum and sub-optimal designs of noise-shaping FIR filters for single- and multi-bit data converters. In the designs, only three parameters, the number of taps, oversampling ratio (OSR) and l1-norm of the filter coefficients are specified, and the in-band peak of the amplitude response is minimized under the specifications. The minimization problem is formulated with the overload-free condition, which guarantees the rigorous stability, and an overload-free converter generates no distortion in any output signals. In the optimum design, the minimization problem is directly and exactly solved, but the sub-optimal method solves this problem by iteratively utilizing the simplex method. The iterative sub-optimal method without the exact optimality is far faster and more efficient than the optimum method. In design examples, optimum and sub-optimal noise-shaping FIR filters for single- and multi-bit data converters are designed, and their optimal performance is revealed. For single-bit data converters with OSR 64, a noise-shaping FIR filter is designed and then shown to achieve a signal to noise and distortion ratio (SNDR) 107.6 [dB] in the band of interest.

Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.

This paper proposes an independent control for parallel-connected multiple uninterruptible power supply (UPS) systems based upon a very simple control scheme. Here, the amplitude and phase angle of the output voltage are the controllable variables. With the only measurement of the output current, the active and reactive components are calculated to define the control variables. The entire system including the equations for the circuit, control and voltage limiters is well represented by a small-signal model, in which the computation of its eigenvalues constitutes the stability proof of the system. The root locus diagram gives an overall panorama of the system performance as a function of a certain gain and it aims to aid the further understanding and the design of the control. The experimental verification is carried out using a mere proportional-integral control scheme, which is a special case of the general control equation used in the theoretical analysis. For some situations, experiments show a flow of lateral current between UPS's, which causes an unbalanced current distribution. By increasing the proportional gain of the control equation for the output voltage amplitude, the lateral current can be substantially suppressed with a consequent improvement of the load sharing. Experimental results under various conditions show excellent results in terms of synchronization, load sharing and stability for three distinct output rating UPS's connected in parallel.

New Recommendation and Future Standards highlight the Power Factor Correction (PFC) converter as a basic requirement for switching power supplies. Most high-frequency power factor correctors use resistor emulation to achieve a near-unity power factor and a small line current distortion. This technique requires forcing the input current with an average-current-mode control to follow the input voltage. Stability of this system was discussed previously by using some linear models. However, in this paper, two nonlinear phenomena have been encountered in the PFC circuit, period doubling bifurcation and chaos. Detection of these new instability phenomena in the stable regions predicted by the prior linear PFC models makes us more susceptible towards them, and reveals the need to consider a nonlinear models. A nonlinear model performing the practical operation of a boost PFC converter has been developed. Then, a simplified and accurate nonlinear model has been proposed and verified experimentally. As a result from this model, instability maps have been introduced to determine the boundary between stable and unstable operating ranges. Then, the period doubling bifurcation has been studied through a new proposed technique based on the capacitor storage energy. It is cleared that, As the load lessens, a required extra storage power is needed to achieve the significant increase in the output voltage. Then, if the PFC system can provide this extra energy, the operation can reach stability with new zero-storage energy else the system will have double-line zero energy that is period doubling bifurcation.

This paper introduces the problem of n mobile agents that repeatedly visit all n nodes of a given network, subject to the constraint that no two agents can simultaneously occupy a node. This paper first presents a self-stabilizing phase-based protocol for a tree network on a synchronous model. The protocol realizes agent traversal with O(Δn) time where n is the number of nodes and Δ is the maximum degree of any vertex in the communication network. The phase-based protocol can also be applied to an asynchronous model and a ring network. This paper also presents a self-stabilizing link-alternator-based protocol with agent traversal time of O(Δn) for a tree network on an asynchronous model. The protocols are proved to be asymptotically optimal with respect to the agent traversal time.