System-level diagnosis is a very important technique for identifying faulty processors in a system with a large number of processors. Processors can test other processors, and then output the test results. The aim of diagnosis is to determine correctly the faulty/fault-free status of all processors. The adaptive diagnosis have been studied in order to perform diagnosis more efficiently. In this paper, we present adaptive diagnosis algorithms for a system modeled by butterfly networks. Our algorithms identify all faulty nodes in butterfly networks with the optimal number of tests. Then, we design another algorithm for diagnosis with very small constant number of rounds.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.

A dual greedy polyhedron is defined by a system of linear inequalities, where the right-hand sides are given by a submodular function and the coefficients matrix is given by the incidence vectors of antichains of a rooted forest. Faigle and Kern introduced this concept and showed that a dual greedy algorithm works for the linear program over dual greedy polyhedra. In this paper, we show that a dual greedy polyhedron is the isomorphic image of an ordinary submodular polyhedron under the Mobius function of the underlying rooted forest. This observation enables us to reduce linear optimization problems over dual greedy polyhedra to those over ordinary submodular polyhedra. We show a new max-min theorem for intersection of two dual greedy polyhedra as well.

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

We will present a novel core mode blocker fabricated with hydrogen loaded Ge-B co-doped fiber exposed to the electric arc discharge using local heat exposure. Tunable bandpass filter based on cascaded LPFGs with a core mode blocker inserted between the LPFGs will be also described. The characteristics are: 6.5-nm bandwidth, 30-nm tuning range, and 15-dB dynamic range, respectively. It can be very useful for application to wavelength stabilization and physical sensors.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

Electron field emission from polycrystalline diamond films has been investigated. Electron emission was measured locally at randomly chosen point on a diamond film fabricated by a microwave plasma chemical deposition method. In the original film, there were some points with a large emission current where flaws were found after the measurements, some points with a small and stable emission current without any flaw, and the other points with no emission. At the point of no emission, the film was electrically broken down by applying a high voltage. After the intentional breaking down, a small and stable emission always appeared there with no flaw. The maximum emission current extracted from an emission site was usually 1µA with no structural flaw found after the measurements. By using a simple model of emission site consisting of a core conductor embedded in insulator, the limitation of emission current is estimated from heating by the current and heat transfer to the insulator.

Multi-channel arrayed waveguide devices are crucial for WDM optical communication systems. Multi-channel arrayed polymer-based waveguide devices have been important for reducing cost and size. This paper introduces two types of multi-channel arrayed polymer-based waveguide devices. We designed and fabricated a four-channel arrayed 22 thermo-optic switch using a low-loss polymer and a four-channel arrayed electro-optic Mach-Zehnder modulator using an electro-optic polymer. The four-channel arrayed 22 thermo-optic switch has very low power consumption and uniform performance. The switching time of the four-channel arrayed EO Mach-Zehnder modulator operating with just lumped electrodes is less than a few nanoseconds.

Electron emissions from single-crystalline diamond surfaces by internally exciting electrons from the valence to conduction bands have been investigated. Monte Carlo simulations have been employed to estimate the impact ionization rates of carriers in diamond under high electric fields up to 1107V/cm. The calculations demonstrate substantial impact ionization rates which rapidly increase with increasing electric fields above 8105V/cm. Highly efficient electron emissions with high emission current efficiencies of approximate unity have been attained from a MIS-type diamond layered structure that are composed of heavily ion-implanted buried layer (M), undoped diamond (I) and hydrogenated p-type diamond (S) with an emission surface of a negative electron affinity. The highly efficient emission mechanism is discussed in relation to the field excitation of electrons from the valence band to the conduction band in the undoped diamond layer and the carrier transport to the diamond surface.

A new algorithm for efficient arithmetic in an optimal extension field is proposed. The new algorithm improves the speeds of multiplication, squaring, and inversion by performing two subfield multiplications simultaneously within a single integer multiplication instruction of a CPU. Our algorithm is used to improve throughputs of elliptic curve operations.

Real traffic flows are captured in various network environments and their statistical properties are analyzed. Based on real traffic flows, MWM (Multifractal Wavelet Model) and Poisson equivalent synthetic traffic flows are generated. Performance analysis of a SB (Synchronous Bulk) packet switch is joined with different types of traffic. Maximum throughput performance of the SB packet switch for various real traffic flows and appropriate MWM and Poisson equivalent synthetic traffic flows are evaluated by using discrete-event simulations. Different flow persistence, SF (Stretch Factor) and scheduling mechanisms are used in order to asses their influence on SB packet switch performance. Traffic asymmetry, either input or output based, has a major influence on SB packet switch performance. By increasing the level of asymmetry, maximum throughput values decrease considerably, especially if the ROT (Rotation) scheduling mechanism is applied. Traffic asymmetry also decreases the influence of the SF parameter on maximum switch throughput. As a general rule of thumb, SF values of no more then 5 must be used if asymmetrical traffic is switched. It is also advisable that OPF (Oldest Packet First) scheduling mechanism is used in such cases. The influence of burstiness and scaling of traffic flows turns out to be relatively insignificant for the SB packet switch maximum throughput results, if the OPF scheduling mechanism is used. Larger throughput discrepancies are detected, if ROT scheduling is used.

Recently, Hwang and Yeh demonstrated that Peyravian-Zunic's password authentication scheme is vulnerable to several attacks, and then proposed a modified version. In this letter, we show that Hwang-Yeh's scheme still has several weaknesses and drawbacks.

This paper presents an innovative 155Mb/s burst-mode laser transmitter chip, which was designed and successfully demonstrated, and contains several new subsystems: a digitally programmed current source, programmable up to 120mA with a resolution of 0.1mA, a fast but accurate intermittent optical level monitoring circuit, and a digital Automatic Power Control (APC) algorithm. This generic and intelligent chip was developed in a standard digital 0.35µm CMOS process. Extensive testing showed a high yield and algorithm stability, as well as excellent performance. During initialization, when the transmitter is connected to the Passive Optical Network (PON) for the first time, maximum three Laser Control Fields (LCF) are needed, with a length of 17bytes (0.88microsecond at 155Mb/s), to stabilize the laser output power. In this short time, the chip can regulate the launched optical output power of any FSAN (Full Service Access Network) compliant laser diode to the required level, even in the extreme circumstances caused by outdoor operation or by battery backup operation during power outages. Other tests show that the chip can further stabilize and track this launched optical power with a tolerance lower than 1dB over a wide temperature range, during the burst mode data transmission. The APC algorithm intermittently adjusts the optical power to be transmitted in a digital way, starting from loosely specified but safe preset values, to the required stable logic "1" and "0" level. No laborious calibration of the laser characteristic curve and storage of the calibration values in lookup tables are needed, nor any off-chip adjustable component. The power consumption is significantly reduced by disabling inactive circuitry and by gating the digital high-speed clock. Although this laser transmitter was developed for FSAN PON applications, which are standardized at a speed of 155Mb/s upstream, the design concept is quite generic and can be applied for developing a wide range of burst mode laser transmitters, such as required for Gigabit PON systems or other TDMA networks.

The Another Solution Problem (ASP) of a problem is the following problem: for a given instance x of and a solution s to it, find a solution to x other than s. The notion of ASP as a new class of problems was first introduced by Ueda and Nagao. They also pointed out that parsimonious reductions which allow polynomial-time transformation of solutions can derive the NP-completeness of ASP of a certain problem from that of ASP of another. In this paper we consider n-ASP, the problem to find another solution when n solutions are given, and formalize it to investigate its characteristics. In particular we consider ASP-completeness, the completeness with respect to the reductions satisfying the properties mentioned above. The complexity of ASPs has a relation with the difficulty of designing puzzles. We prove the ASP-completeness of three popular puzzles: Slither Link, Cross Sum, and Number Place. Since ASP-completeness implies NP-completeness, these results can be regarded as new results of NP-completeness proof of puzzles.

We propose a new scheme of indoor optical wireless LAN based on a special CMOS image sensor (CIS), which realizes a low-power compact communication module with large uplink capacity due to space division multiple access. In our scheme, all nodes and a hub utilize the CIS as a photoreceiver as well as a position-sensing device for finding the positions of the communication modules, while a single large photodiode is used in the conventional systems. Although conventional image sensors cannot detect modulated signals because they integrate photocurrents, our CIS has a high-speed readout function for receiving optical data from the specific pixels receiving optical signals. The advantages of the proposed scheme are 1) compact embodiment of the communication module due to no need of the bulky mechanical components for searching the other modules, 2) space division multiple access, which leads to 3) large capacity of uplink, and 4) applicability of simple modulation and coding schemes for optical signals. In our scheme, diffusive and narrow beam lights are complementally used for position detection and communication, respectively, which leads to the advantage 5) low power consumption of both light emitter and receiver circuits. To demonstrate two basic functional modes of our CIS: an IS (image sensor) mode and a COM (communication) mode, we fabricate an 88-pixel CIS by use of a 0.8µm BiCMOS technology. In the experiments, the image of a light source is successfully captured in the IS mode for integration time of 29.6msec and optical power of 1.1nW. After the functional mode of the pixel receiving the light is changed to the COM mode, the eye pattern of the modulated light is obtained from the pixel at frequency of 1MHz. We also fabricate a test pixel circuit with in-pixel amplifier, with which operation speed is improved to 100MHz.

Bidirected graphs which are generalizations of undirected graphs, have three types of edges: (+,+)-edges, (-,-)-edges and (+,-)-edges. Undirected graphs are regarded as bidirected graphs whose edges are all of type (+,+). The notion of perfection of undirected graphs can be naturally extended to bidirected graphs in terms of polytopes. The fact that a bidirected graph is perfect if and only if the undirected graph obtained by replacing all edges to (+,+) is perfect was independently proved by several researchers. This paper gives a polyhedral proof of the fact and introduces some new knowledge on perfect bidirected graphs.

The conventional describing function of Coulo-mb friction is based on the assumption that the reference input is constant. The author proposes the describing function of Coulomb friction for the ramp reference input. The experimental results for the DC servo motor control system with ramp tracking controller are shown.

Some of the recent digital systems have a serious clock skew problem due to huge hardware implementation and high-speed operation in VLSI's. To overcome this problem, clock distribution techniques and, more notably, asynchronous system design methodologies have been investigated. Since the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present a design of asynchronous digital system which is based on B-ternary logic that can process binary data. The system which is based on speed-independent mode consists of data-path and its controller. Then we provide B-ternary two-phase binary data processing in the data-path and its control procedure with hand-shake protocol. To implement the system some functional elements are presented, that is, a ternary-in/binary-out register with request/acknowledge circuits and a control unit. These functional elements are fabricated with ternary NOR, NAND, INV gates and ternary-in/binary-out D-FF (D-elements). The B-ternary based asynchronous circuit has less interconnections, achives race-free operations and makes use of conventional binary powerful design tools. Particularly, we extend the speed-independent delay model to relativity delays in order to reduce hardware overhead of checking memory stability in the system. As a concrete example, a carry-completion type asynchronous adder system is demonstrated under extended speed-independent mode to show the validity of the extension.

In this paper we present reconfigurable computing as a compelling choice of computing platform for real-time, onboard processing for satellite applications. In particular, we discuss the use of reconfigurable computing in the context of a real-time remote sensing system, providing motivation for such a system and describing attributes of reconfigurable computing that support it as the technology of choice. The High Performance Computing (HPC-I) payload, designed and developed for the Australian scientific satellite FedSat, is introduced as a demonstration of onboard processing in space using reconfigurable logic. We present an overview of the real-time remote sensing system architecture, and describe the design and implementation of three remote sensing algorithms in HPC-I for cloud masking, wildfire detection and volcanic plume detection. Finally, results from simulation and testing are presented which show very promising performance in terms of data throughput and detection capabilities.

The achievable rate region related to the problem of generating mutually independent random sequences is determined. Furthermore, it is proved that the output distribution of lossless source encoders with correlated side information is asymptotically independent of the side information. Based on this, we can realize a random number generator that produces mutually asymptotically independent random sequences from random sequences emitted from correlated sources.