We have formed simple polarization-controller arrays by inserting liquid crystal (LC) in trenches cut across planar lightwave circuits (PLCs). We fabricated LC layers for use as polarization controllers on PLCs in two ways; in one, the ultra-thin layer of LC is held in a cell that is inserted into a trench on the PLC while in the other, the trench is directly filled with the LC. The ultra-thin LC cell can change the phase of 1.55-µm light from 0 to 3π while the LC filling can change the phase of light at the same wavelength from 0 to 12π below 5Vrms. Two former parallel-aligned ultra-thin LC cells, where the directions of alignment of the liquid crystals are rotated by 45 relative to each other, are capable of converting light with an arbitrary input polarization to TE or TM polarization. Ultra-thin cells of twisted nematic LC can switch the polarization between TE and TM modes with an extinction ratio of -15dB. The array we fabricated had a pitch of 1 mm and 5 elements, but an array with more than 100 elements and a pitch below 125µm will easily be possible by using finely patterned transparent electrodes. We have also applied our techniques to the fabrication of LC-based variable optical attenuators (VOA) on the PLC.

This paper studies the necessity of local CFAR processing in CFAR detection with multisensors. This necessity is shown by comparison between centralized CFAR detection and the distributed CFAR detection scheme based on local CFAR processing, under three typical backgrounds and in several cases of mismatching ρ, the relative ratio of local clutter power level in sensors in a homogeneous background. Results show that centralized CFAR processing can not be considered as CFAR without exact prior knowledge of ρ. In addition, even if the knowledge of ρ is available, the great difference among local clutter power levels can also result in severe performance degradation of centralized CFAR processing. In contrast, the distributed CFAR detection based on local CFAR processing is not affected by ρ at all, a fact which was proposed in a previous published paper. Therefore, the CFAR processing must be made locally in sensors for CFAR detection with multisensors.

Control scheme for accurately optimizing (and also automatically stabilizing) the interferometer phase bias of Symmetric-Mach-Zehnder (SMZ)-type ultrafast all-optical switches is proposed. In this control scheme, a weak cw light is used as a supervisory input light and its spectral power ratio at the switch output is used as a bipolar error signal. Our experimental result at 168-Gb/s 16:1 demultiplexing with a hybrid-integrated SMZ switch indicates the feasibility and the sensitivity of this control scheme.

Multi-channel arrayed waveguide devices are crucial for WDM optical communication systems. Multi-channel arrayed polymer-based waveguide devices have been important for reducing cost and size. This paper introduces two types of multi-channel arrayed polymer-based waveguide devices. We designed and fabricated a four-channel arrayed 22 thermo-optic switch using a low-loss polymer and a four-channel arrayed electro-optic Mach-Zehnder modulator using an electro-optic polymer. The four-channel arrayed 22 thermo-optic switch has very low power consumption and uniform performance. The switching time of the four-channel arrayed EO Mach-Zehnder modulator operating with just lumped electrodes is less than a few nanoseconds.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

TLSP (Thread-Level Speculative Parallel processing) architecture is a growing processor architecture. Parallelism of a program executed on this architecture is ruled by the combination of techniques which relax data dependences. In this paper, we evaluate the limits of parallelism of the TLSP architecture by using abstract machine models. We have three major results. First, if we use solely each technique which relaxes data dependences, "renaming" has a large effect on the TLSP architecture. Second, combinatorial use of "memory disambiguation" and "renaming" leads to huge parallelism. Third, constant effects are obtained by concurrent use of "value prediction" and other techniques.

Our work introduces a speech enhancement algorithm that modifies on-line the spectral representation of degraded speech to approximate the spectral coefficients of high quality speech. The proposed framework is based on the application of Discrete Fourier Transform (DFT) to a large ensemble of clean speech frames and the estimation of parametric, heavy-tail non-Gaussian probability distributions for the spectral magnitude. Each clean spectral band possesses a unique pdf. This is selected according to the smallest Kullback-Leibler divergence between each candidate heavy-tail pdf and the non-parametric pdf of the magnitude of each spectral band of the clean ensemble. The parameters of the distributions are derived by Maximum Likelihood Estimation (MLE). A maximum a-posteriori (MAP) formulation of the degraded spectral bands leads to soft threshold functions, optimally derived from the statistics of each spectral band and effectively reducing white and slowly varying coloured Gaussian noise. We evaluate the new algorithm on the task of improving the quality of speech perception as well as Automatic Speech Recognition (ASR) and demonstrate its robustness at SNRs as low as 0 dB.

Electron field emission from polycrystalline diamond films has been investigated. Electron emission was measured locally at randomly chosen point on a diamond film fabricated by a microwave plasma chemical deposition method. In the original film, there were some points with a large emission current where flaws were found after the measurements, some points with a small and stable emission current without any flaw, and the other points with no emission. At the point of no emission, the film was electrically broken down by applying a high voltage. After the intentional breaking down, a small and stable emission always appeared there with no flaw. The maximum emission current extracted from an emission site was usually 1µA with no structural flaw found after the measurements. By using a simple model of emission site consisting of a core conductor embedded in insulator, the limitation of emission current is estimated from heating by the current and heat transfer to the insulator.

A configurable device "PCA-Chip2" implements the concept of Plastic Cell Architecture, which is an extension of programmable logic devices. This paper presents basic design tools for the PCA-Chip2 as the first step to develop the total design environment. Given a C description of a target function, configuration data for PCA-Chip2 is automatically generated by the tools. Trial designs by the tools are also presented to demonstrate the practicability of the proposed approach.

We present a new multi-stage charge pump that is suitable for low-voltage operation, and in particular for low voltage flash memory. Compare to the Dickson charge pump and previously reported modified Dickson charge pumps, the proposed charge pump offers the improved pumping voltage gains. The proposed charge pump is composed of a pair of pumps and utilizes the internal boosted voltages of one side of the paired pumps as the charge transferring voltages to the other side. The simulated and measured results indicate that the proposed pump is highly efficient in overcoming both the pumping gain decrease and the current driving capability degradation caused by the threshold voltage of the charge-transfer gate.

Electron emissions from single-crystalline diamond surfaces by internally exciting electrons from the valence to conduction bands have been investigated. Monte Carlo simulations have been employed to estimate the impact ionization rates of carriers in diamond under high electric fields up to 1107V/cm. The calculations demonstrate substantial impact ionization rates which rapidly increase with increasing electric fields above 8105V/cm. Highly efficient electron emissions with high emission current efficiencies of approximate unity have been attained from a MIS-type diamond layered structure that are composed of heavily ion-implanted buried layer (M), undoped diamond (I) and hydrogenated p-type diamond (S) with an emission surface of a negative electron affinity. The highly efficient emission mechanism is discussed in relation to the field excitation of electrons from the valence band to the conduction band in the undoped diamond layer and the carrier transport to the diamond surface.

We demonstrate a multi-wavelength (40WDM 10Gbit/s) optical packet router capable of processing 4 Gigapackets/s based on all-optical label generation and recognition using 16-bit, 20Gbit/s four-level phase coding superstructure fibre Bragg gratings. Error free operation is obtained for the switched packets when all 40 channels are transmitting simultaneously.

The purpose of this paper is to discuss length estimation based on digitized curves. Information on a curve in the Euclidean plane is lost after digitization. Higher resolution supports a convergence of a digital image towards the original curve with respect to Hausdorff metric. No matter how high resolution is assumed, it is impossible to know the length of an original curve exactly. In image analysis we estimate the length of a curve in the Euclidean plane based on an approximation. An approximate polygon converges to the original curve with an increase of resolution. Several approximation methods have been proposed so far. This paper proposes a new approximation method which generates polygonal curves closer (in the sense of Hausdorff metric) in general to its original curves than any of the previously known methods and discusses its relevance for length estimation by proving a Convergence Theorem.

Let α and β be polygons with the same area. A Dudeney dissection of α to β is a partition of α into parts which can be reassembled to produce β in the following way. Hinge the parts of α like a chain along the perimeter of α, then fix one of the parts and without turning the pieces over, rotate the remaining parts about the fixed part to form β in such a way that the entire perimeter of α is in the interior of β and the perimeter of β consists of the dissection lines formerly in the interior of α . In this paper we discuss a special type of Dudeney dissection of convex polygons in which α is congruent to β and call it a congruent Dudeney dissection. In particular, we consider the case where all hinge points are interior to the sides of the polygon α. A convex polygon which has a congruent Dudeney dissection is called a chameleon. We determine all convex polygons which are chameleons.

The one dimensional cutting stock problem (1D-CSP) is one of the representative combinatorial optimization problems, which arises in many industries. As the setup costs of cutting patterns become more dominant in recent cutting industry, we consider a variant of 1D-CSP, in which the total number of applications of cutting patterns is minimized under the constraint that the number of different cutting patterns is specified in advance. We propose a local search algorithm that uses the neighborhood obtained by perturbating one cutting pattern in the current set of patterns, where the perturbations are done by utilizing the dual solution of the auxiliary linear programming problem (LP). In this process, in order to solve a large number of LPs, we start the criss-cross variation of the simplex algorithm from the optimal simplex tableau of the previous solution, instead of starting it from scratch. According to our computational experiment, it is observed that the proposed algorithm obtains a wide variety of good solutions which are comparable to the existing heuristic approaches.

We propose a novel method of precisely measuring the polarization dependence of single pass gain (PDG) in a semiconductor optical amplifier integrated with spot-size convertors (SS-SOA). By averaging the signal gain of a SS-SOA over a wide wavelength range using the amplified spontaneous emission (ASE) of an erbium doped fiber (EDF), the PDG can be accurately estimated. This is because the influence of gain ripples on the measurement results are drastically reduced. We successfully evaluated the PDG of an angled-facet SS-SOA, even before the process of anti-reflection coating, within a small error of 0.5dB. The EDF-ASE technique is useful in sampling tests and selecting angled-facet SS-SOA chips from wafers. The polarization dependence of the coupling efficiency (PDCE) between a SS-SOA and optical fiber is also evaluated by measuring the photo-current of the active layer for TE and TM input signals. It is possible, therefore, to specify the polarization characteristics of the active region and spot-size converter region, which are indispensable parameters for the design of the SS-SOA.

Recently, Hwang and Yeh demonstrated that Peyravian-Zunic's password authentication scheme is vulnerable to several attacks, and then proposed a modified version. In this letter, we show that Hwang-Yeh's scheme still has several weaknesses and drawbacks.

We propose a new closed-loop power control scheme for wireless mobile communication systems using an adaptive step size. The proposed scheme selects the basic power control step size by considering the speed of the mobile station and a variable step size by using instantaneous companding logic based on power control command bit patterns. We show its improved performance in view of the standard deviation of received power at the base station in consideration of channel BER.

This paper presents an innovative 155Mb/s burst-mode laser transmitter chip, which was designed and successfully demonstrated, and contains several new subsystems: a digitally programmed current source, programmable up to 120mA with a resolution of 0.1mA, a fast but accurate intermittent optical level monitoring circuit, and a digital Automatic Power Control (APC) algorithm. This generic and intelligent chip was developed in a standard digital 0.35µm CMOS process. Extensive testing showed a high yield and algorithm stability, as well as excellent performance. During initialization, when the transmitter is connected to the Passive Optical Network (PON) for the first time, maximum three Laser Control Fields (LCF) are needed, with a length of 17bytes (0.88microsecond at 155Mb/s), to stabilize the laser output power. In this short time, the chip can regulate the launched optical output power of any FSAN (Full Service Access Network) compliant laser diode to the required level, even in the extreme circumstances caused by outdoor operation or by battery backup operation during power outages. Other tests show that the chip can further stabilize and track this launched optical power with a tolerance lower than 1dB over a wide temperature range, during the burst mode data transmission. The APC algorithm intermittently adjusts the optical power to be transmitted in a digital way, starting from loosely specified but safe preset values, to the required stable logic "1" and "0" level. No laborious calibration of the laser characteristic curve and storage of the calibration values in lookup tables are needed, nor any off-chip adjustable component. The power consumption is significantly reduced by disabling inactive circuitry and by gating the digital high-speed clock. Although this laser transmitter was developed for FSAN PON applications, which are standardized at a speed of 155Mb/s upstream, the design concept is quite generic and can be applied for developing a wide range of burst mode laser transmitters, such as required for Gigabit PON systems or other TDMA networks.