Multi-recast techniques make it possible for a voter to participate in a sequence of different designated votings by using only one ticket. In a multi-recastable ticket scheme for electronic voting, every voter of a group can obtain an m-castable ticket (m-ticket), and through the m-ticket, the voter can participate in a sequence of m different designated votings held in this group. The m-ticket contains all possible intentions of the voter in the sequence of votings, and in each of the m votings, a voter casts his vote by just making appropriate modifications to his m-ticket. The authority cannot produce both the opposite version of a vote cast by a voter in one voting and the succeeding uncast votes of the voter. Only one round of registration action is required for a voter to request an m-ticket from the authority. Moreover, the size of such an m-ticket is not larger than that of an ordinary vote. It turns out that the proposed scheme greatly reduces the network traffic between the voters and the authority during the registration stages in a sequence of different votings, for example, the proposed method reduces the communication traffic by almost 80% for a sequence of 5 votings and by nearly 90% for a sequence of 10 votings.

This paper presents a finite buffer M/G/1 queue with two classes of customers who are served by a combination of head-of-the-line priority and buffer reservation schemes. This combination gives each class of customers high or low priorities in terms of both delay and loss. The scheme is analyzed for the model in which one class of customers has high priorities over the other class of customers with respect to both delay and loss. First, steady-state joint probability distribution of the number of each class of customers in the buffer and remaining service time is derived by a supplementary variable method. Second, loss probability and mean waiting time for each class of customers are provided using this probability distribution. Finally, a combination of head-of-the-line priority and buffer reservation schemes is numerically compared with other buffer management schemes in terms of admissible offered load to show its effectiveness under differing QoS requirements.

The post-annealing process has been investigated for (Ba, Sr)TiO3 [BST] thin films employed as a capacitor dielectric in 1 Gbit dynamic random access memories (DRAMs). The effects of post-annealing on morphology, crystallinity, and dielectric properties were examined for thin film capacitors with BST prepared on Pt electrodes by liquid source chemical vapor deposition (CVD). The direct annealing of BST capacitors caused a roughening in surface morphology of the upper Pt electrodes and BST films. However, the post-annealing of capacitors with a silicon dioxide passivation layer was found to cause little change in surface morphology of Pt and BST, and also no significant deterioration in leakage current. The improvement in crystallinity of BST films through post-annealing was confirmed at a temperature in the range 700-850 by X-ray diffraction (XRD) and transmission electron microscope (TEM). Moreover, the post-annealing experiments for BST films with different compositions showed that the post-annealing greatly increases the dielectric constant of BST films having approximately stoichiometric composition. The leakage and breakdown properties of BST films were also examined, indicating that excess Ti ions result in an increase of the turn-on voltage and the breakdown time. Based on these investigations, the electrical properties of dielectric constant ε 260, equivalent silicon dioxide thickness teq 0. 44 nm, and leakage current JL110-7 A/cm2 at 1. 9 V were successfully obtained for stoichiometric 30-nm-thick BST films post-annealed at 750. Hence, it can be concluded that the post-annealing is a promising technique to enhance the applicability of CVD-deposited BST films with conformal coverage to memory cell capacitors of 1 Gbit DRAMs.

In many applications, information retrieval is a very important research field. In several key strategies, the binary trie is famous as a fast access method able to retrieve keys in order. Especially, a Patricia trie gives the shallowest trie by eliminating all nodes which have only one arc, and it requires the smallest storage among the other trie structures. If trie structures are implemented, however, the greater the number of the registered keys, the larger storage is required. In order to solve this problem, Jonge et al. proposed a method to change the normal binary trie into a compact bit stream. This paper proposes the improved trie representation for the Patricia trie, as well as the methods for searching and inserting the key on it. The theoretical and experimental results, using 50,000 Japanese nouns and 50,000 English words, show that this method generates 25-39 percent shorter bit streams than the traditional method. This method, thus, enables us to provide more compact storage and faster access than the traditional method.

In this paper, we propose a new structure of the frequency domain adaptive filter (FDAF). The proposed structure is based on the modified DFT pair which consists of the FIR filters, so that un-delayed output signal can be obtained with stable convergence and without accumulated error which are problems for the conventional FDAFs. The convergence performance of the proposed FDAF is examined through the computer simulations in the adaptive line enhancer (ALE) comparing with the conventional FDAF and the DCT domain adaptive filter. Furthermore, in order to improve the error performance of the FDAF, we propose a composite algorithm which consists of the normalized step size algorithm for fast convergence and the variable step size one for small estimation error. The advantage of the proposed algorithm is also confirmed through simulations in the ALE. Finally, we propose a reduction method of the computational complexity of the proposed FDAF. The proposed method is to utilize a part of the FFT flow-graph, so that the computational complexity is reduced to O(N log N).

In a distributed concurrent system such as a computer communication network, the system components communicate with each other via communication links in order to accomplish a desired distributed application. If the links are dynamically established among the components, the system configuration as well as its behavior becomes complex. In this paper, we give formal specification of such a dynamically reconfigurable system in which the components are modeled by communicating finite state machines executed concurrently with the communication links which are dynamically established and disconnected. We also present an algorithm to validate the safety and link-related properties in the specified behavior. Finally, we design and implement a simulator and a validator that enables execution and validation of the given specification, respectively.

Using transmission electron microscopy (TEM), we studied structural defects in a Sr0. 7Bi2. 3Ta2O9 (SBT) thin film to be used for ferroelectric memory devices. We examined the effects of the substrate, crystal continuity, and dislocations in crystals as major causes of defects. For this study, we used an SBT thin film grown from an alkoxide solution. Since crystal growth was hardly influenced by the substrate, the substrate had little influence on the occurrence of defects resulted in misfit of lattice constant. Regions of partially low crystal continuity were observed in the SBT thin film. In these regions, the orientation was still uniform, but the continuity of the crystal grain was low because of the defects. In addition, variation in contrast was observed in the crystals, however, no obvious variation in chemical composition was found in this region of varying contrast. Therefore, the contrast variation is considered to be attributed to the dislocation. Such a dislocation was found to be occurred in the direction of the (2010) plane in many instances. The defects in the SBT film were also confirmed by the TEM observation.

This paper describes a realtime cell-loss ratio evaluation algorithm for ATM connection admission control. This algorithm gives an efficient evaluation of cell-loss ratio from traffic descriptors such as peak cell rate, sustainable cell rate, and maximum burst size for each VC. The most remarkable characteristics of this algorithm are that it terminates within a millisecond and that its time is independent of both the number of VCs and the capacity of a cell buffer.

In this paper, a new variable length code transmission technique utilizing multicode DS/SS is proposed. A common problem associated with the use of variable length codes over wireless channels is loss of synchronization due to bit inversion caused by channel noise. The loss of synchronization produces burst errors in the received source symbols. The proposed system assigns multiple spreading codes to a single user to transmit variable length codes. The number of the spreading codes is equal to the maximum bit length of the codewords. All the bits of the codeword are spread and transmitted at one time by utilizing the assigned multiple spreading codes. Therefore no synchronization of the codeword is required. This paper evaluates the performance of the proposed technique over an AWGN channel and a Rayleigh fading channel. Our results show that the proposed technique improves the symbol error rate (SER) performance by 2-3 dB on the AWGN channel and 10-20 dB on the Rayleigh fading channel as compared with a conventional transmission technique. The source-channel coding suitable for the proposed technique improves the performance by another 15 dB on the Rayleigh fading channel. The proposed transmission technique works even in a low Es/No region.

A more judicious choice of trial functions to implement the Improved Circuit Theory (ICT) application to multi-element antennas is achieved. These new trial functions, based on Tai's modified variational implementation for single element antennas, leads to an ICT implementation applicable to much longer co-planar dipole arrays. The accuracy of the generalized impedance formulas is in good agreement with the method of moments. Moreover, all these generalized formulas including the radiation pattern expressions are all in closed-form. This leads to an ICT implementation which still requires much shorter CPU time and lesser computer storage compared to method of moments. Thus, for co-planar dipole arrays, the proposed implementation presents a relatively very efficient method and would therefore be found useful in applications such as CAD/CAE systems.

This paper studies a congestion control scheme in integrated variable bit-rate video, audio and data (e. g. , image or text) communications, where each video stream is synchronized with the corresponding audio stream. When the audio and video streams are output, media synchronization control is performed. To avoid congestion, we employ a dynamic video resolution control scheme which dynamically changes the video encoding rate according to the network loads. By simulation, the paper evaluates the performance of the scheme in terms of throughput, loss rate, average delay, and mean square error of synchronization. Numerical results show the effectiveness of the scheme.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.

Requirements engineering refers to activities of gathering and organizing customer requirements and system specifications, making explicit representations of them, and making sure that they are valid and accounted for during the course of the design lifecycle of software. One very popular software development practice is the incremental development practice. The incremental development refers to practices that allow a program, or similarly specifications, to be developed, validated, and delivered in stages. The incremental practice is characterized by its depth-first process where focuses are given to small parts of the system in sequence to fair amounts of detail. In this paper, we present a development and validation of specifications in such an incremental style using a tool called ASADAL, a comprehensive CASE tool for real-time systems. ASADAL supports incremental and hierarchical refinements of specifications using multiple representational constructs and the evolving incomplete specifications can be formally tested with respect to critical real time properties or be simulated to determine whether the specifications capture the intended system behavior. In particular, we highlight features of ASADAL's specification simulator, called ASADAL/SIM, that plays a critical role in the incremental validation and helps users gain insights into the validity of evolving specifications. Such features include the multiple and mixed level simulation, real-value simulation, presentation and analysis of simulation data, and variety of flexible simulation control schemes. We illustrate the overall process using an example of an incremental specification development of an elevator control system.

A field theory for geometrical pattern identification is developed based on the postulate that various modified patterns are identified via invariant characteristics of pattern transformations. The invariant characteristics of geometrical patterns are written as the functional of the light intensity distribution of pattern, its spatial gradient, and also its spatial curvature. Some definite expressions of the invariant characteristic functional for two dimensional linear transformation are derived, and their invariant and feature extracting property are examined numerically. It is also shown that the invariant property is conserved even when patterns are deformed locally by introducing a "gauge field" as new degree of freedom in the functional in form of a covariant derivative. Based on this idea, we discuss a field theoretical model for pattern identification performed in biological systems.

This paper deals with an orthogonal functional expansion of a non-linear stochastic functional of a stationary binary sequence taking 1 with unequal probability. Several mathematical formulas, such as multivariate orthogonal polynomials, recurrence formula and generating function, are given in explicit form. A formula of an orthogonal functional expansion for a stochastic functional is presented; the completeness of expansion is discussed in Appendix.

Predicting the performance of high speed wide area ATM networks (WANs) is a difficult task. Evaluating the performance of these systems by means of mathematical models is not yet feasible. As a result, the creation of simulation models is usually the only means of predicting and evaluating the performance of such systems. In this paper, we use measurements to validate simulation models of TCP/IP over high speed ATM wide area networks. Validation of simulations with measurements is not common; however, it is needed so that simulation models can be used with confidence to accurately characterize the performance of ATM WANs. In addition, the appropriate level of complexity of the simulation models needs to be determined. The results show that under appropriate conditions simulation models can accurately predict the performance of complex high speed ATM wide area networks. This work also shows that the user perceived performance is dependent on host processing demands.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

We propose ATM switching nodes with a feedback rate control scheme, AREX, which does not require a large buffer space and does not deteriorate throughput even in large-scale and high-speed ATM-WANs. The goal of our study is to establish the ATM multi-protocol emulation network ALPEN, which is an ATM-WAN architecture for establishing a backbone for multimedia networks. ALPEN achieves an ATM-WAN which is robust against long propagation delays. It also provides high performance without a large buffer space in an ATM-WAN environment. In ALPEN, each transit node informs the edge nodes only its residual bandwidth ratio. The edge nodes support multiple ATM-layer services by emulating them based on the information notified by transit nodes. Our research has been directed towards achieving high performance ABR (Available Bit Rate) service in an ATM-WAN by using ALPEN. The conventional ABR service requires transit nodes to have relatively high calculation power and large buffer space to overcome the effect of the long propagation delays common in WANs. ALPEN node systems have been developed for trials with actual network traffic. ALPEN with AREX reduces the calculation load of transit nodes for ABR service. That is confirmed by the size of the DSP program created for a test system. ALPEN with AREX is, therefore, able to emulate ABR service with higher performance in ATM-WANs, because ALPEN edge nodes are able to indicate the users allowed by ER (Explicit Rate) feedback. The network throughput, maximum queue length at congestion point, and burst transmission rate are determined by simulation. ALPEN with AREX achieves better performances than the conventional ABR network.

Although ATM networks support various traffic requirements, but many data applications are unable to precisely specify traffic parameters such as bit rate. These applications generally require a dynamic share of the available bandwidth among all active connections, they are called available-bit-rate (ABR) service. Due to bursty and unpredictable pattern of an ABR data stream, its traffic control is more challenging than other services. In this paper, we present an improved ABR traffic control approach, called Offset Proportional Rate Control Algorithm (OPRCA). The proposed approach achieves high link utilization, low delay and weighted fair sharing among contenting sources according to the predefined OPR. The implementation is much simpler than that of existing schemes. OPRCA combines an end-to-end rate control with link-by-link feedback control, and employs a buffering scheme that avoids Head-of-Line (HOL) blocking. It can dynamically regulate the transmission rate of source traffic and maintain the real fairness among all active connections. Simulation results have shown the effectiveness of OPRCA in several performance aspects.

This letter proposes a Perfect-Reconstruction (PR) encryption scheme based on a PR QMF bank. Using the proposed scheme, signals can be encrypted and reconstructed perfectly by using two Periodically Time-Varying (PTV) digital filters respectively. Also we find that the proposed scheme has a "good" encryption effect and compares favorably with frequency scramble in the aspects of computation complexity, PR property, and degree of security.