With the knowledge of the syndromes Sa,b, 0a,b q-2, the exact error values cannot be determined by using the conventional (q-1)2-point discrete Fourier transform in the decoding of a plane algebraic-geometric code over GF(q). In this letter, the inverse q-point 1-dimensional and q2-point 2-dimensional affine Fourier transform over GF(q) are presented to be used to retrieve the actual error values, but it requires much computation efforts. For saving computation complexity, a modification of the affine Fourier transform is derived by using the property of the rational points of the plane Hermitian curve. The modified transform, which has almost the same computation complexity of the conventional discrete Fourier transform, requires the knowledge of syndromes Sa,b, 0 a,b q-2, and three more extended syndromes Sq-1,q-1, S0,q-1, Sq-1,0.

The additive noise response of a charge pump phase-locked loop in the synchronous mode of operation has been studied. In order to determine the tracking and noise performances of the loop, mean square values of tracking error and local oscillator phase jitter have been analytically obtained. Analytical results agree well with the simulation results obtained here and elsewhere. The analysis performed can be used in choosing different system parameters for optimum system operation.

The minimum mean-squared error (MMSE) linear detector has been proposed to successfully suppress the multiple access interference and mitigate the near-far problem in direct-sequence code-division multiple access communication systems. In the presence of unknown or time-varying channel parameters, the MMSE linear detector can be implemented by the blind Griffiths' algorithm, which uses the desired signal vector instead of a training sequence of symbols for initial adaptation. In this paper, a variable step-size (VSS) Griffiths' algorithm is proposed for accelerating the convergence speed, especially in the presence of strong interference. Numerical results show that the convergence properties of the VSS Griffiths' algorithm are robust against the wide eigenvalue-spread problem of the correlation matrix associated with the received signal vector compared to the Griffiths' algorithm using a fixed step-size.

This paper clarifies two variable-to-fixed length codes which achieve optimum large deviations performance of empirical compression ratio. One is Lempel-Ziv code with fixed number of phrases, and the other is an arithmetic code with fixed codeword length. It is shown that Lempel-Ziv code is asymptotically optimum in the above sense, for the class of finite-alphabet and finite-state sources, and that the arithmetic code is asymptotically optimum for the class of finite-alphabet unifilar sources.

We consider the optimal average cost of variable length source code averaged with a given probability distribution over source messages. The problem was argued in Csiszar and Korner's book. In a special case of binary alphabet, we find an upper bound to the optimal cost minus an ideal cost, where the ideal cost is the entropy of the source divided by a unique scalar that makes negative costs logarithmic probabilities. Our bound is better than the one given in the book.

This paper proposes a novel MAC scheme over APON based on the cell arrival timing information to provide residential and small business customers with multimedia services. The proposed scheme supports the frame format of ITU-T recommendation G.983 and also provides diverse ATM service classes such as CBR, rtVBR, nrtVBR, ABR, and UBR traffics. Each service is allocated on the basis of priority and cell arrival timing information. Especially, the CBR and rtVBR services, which are sensitive to delay and CDV, are allocated with higher priority and more exact arrival timing resolution which is achieved with specific coding and ranging procedure. For the proposed MAC scheme, we present grant field format, minislot format, and bandwidth allocation algorithm. Computer simulation results show that the performance of the proposed scheme is significantly improved in terms of CDV and delay time in case of CBR and rtVBR services, comparing with the normal FIFO scheme.

Experiment is reported of enhanced backscattering of light in binary and ternary suspensions of rutile and/or alumina particles. With a conventional CCD camera system for observing the phenomena, the angular line shape and the enhancement factor were agreed with the theoretically predicted curve and value. Observation of the angular distribution scattered at the backscattered direction supported the hypothesis proposed by Pine et al. , in which the transport mean free path of the polydisperse mixture can be expressed in terms of summing its reciprocal values weighted over the particle sizes.

In this paper, we focus on regularity and set-valued functions. Regularity was first introduced by S. C. Kleene in the propositional operations of his ternary logic. Then, M. Mukaidono investigated some properties of ternary functions, which can be represented by regular operations. He called such ternary functions "regular ternary logic functions". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states or initial states in binary logic circuits that Boolean functions cannot cope with. Furthermore, they are also applied to studies of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions into r-valued set-valued functions, which are defined as mappings on a set of nonempty subsets of the r-valued set {0, 1, . . . , r-1}. First, the paper will show a method by which operations on the r-valued set {0, 1, . . . , r-1} can be expanded into operations on the set of nonempty subsets of {0, 1, . . . , r-1}. These operations will be called regular since this method is identical with the way that Kleene expanded operations of binary logic into his ternary logic. Finally, explicit expressions of set-valued functions monotonic in subset will be presented.

In 1995, 8 kb/s CS-ACELP coder of G.729 is standardized by ITU-T SG15 and it has been reported that the speech quality of G.729 is better than or equal to that of 32 kb/s ADPCM (G.726). However G.729 is the fixed rate speech coder, and it does not consider the property of voice activity in mutual conversation. If we use the voice activity, we can reduce the average bit rate in half without any degradations of the speech quality. In this paper, we propose an efficient variable rate algorithm for G.729. The variable rate algorithm consists of two main subjects, the rate determination algorithm and the design of sub rate coders. For the robust VAD algorithm, we combine the energy-thresholding method, the phonetic segmentation method by integration of various feature parameters obtained through the analysis procedure, and the variable hangover period method. Through the analysis of noise features, the 1 kb/s sub rate coder is designed for coding the background noise signal. Also, we design the 4 kb/s sub rate coder for the unvoiced parts. The performance of the variable rate algorithm is evaluated by the comparison of speech quality and average bit rate with G.729. Subjective quality test is also done by MOS test. Conclusively, it is verified that the proposed variable rate CS-ACELP coder produces the same speech quality as G.729, at the average bit rate of 4.4 kb/s.

This paper investigates the performance of relative rate (RR) switch algorithms for available bit rate (ABR) flow control in asynchronous transfer mode (ATM) networks. An RR switch can be implemented differently according to the congestion detection and notification methods used. This paper proposes three implementation schemes for an RR switch using various congestion detection and notification methods, and then analyzes the allowed cell rate (ACR) of a source and the queue length at a switch in steady state. The upper and lower bounds for the maximum and minimum queue lengths are also determined for each scheme, respectively, thereby investigating the effects of ABR parameter values on a queue length. Furthermore, a selection method for rate increase factor (RIF) and rate decrease factor (RDF) parameter values is suggested to prevent buffer overflow and underflow.

Hφholdt, van Lint and Pellikaan proposed a generalization of one-point AG codes, called the evaluation codes. We show that an evaluation code from a weight function can be constructed as Miura's generalization of one-point AG codes. Hence we can construct a one-point AG code as good as a given evaluation code from a weight function.

We propose and analyze a traffic model of a cellular radio communication network with an arbitrary cell connection and arbitrary probabilistic movement of mobiles between the cells. Our analytic model consists of birth-and-death processes for individual cells connected by the numerical adjustment of hand-off rates. This approximation is validated by simulation. We evaluate the probabilities of the immediate loss, the completion, and the forced termination during hand-off for an arbitrary call in the network. Our numerical examples reveal the cases in which the increase in the generation rate of new calls results in the increase in the loss probability without affecting much the probability of forced termination in a limited service area.

A new asynchronous transfer mode adaptation layer (AAL), called AAL2, is being designed mainly for low-bit-rate voice traffic, and nodes that can assemble and disassemble AAL2 cells are being developed to make AAL2 usage efficient. This paper investigates the delay and performance of AAL2 nodes by an analytical method. Then, using the results, it analyzes a network using AAL2 nodes and shows the bandwidth reduction achieved by using AAL2 switching nodes as transit nodes.

When we have a singular Cab curve with many rational points, we had better to construct linear codes on its normalization rather than the original curve. The only obstacle to construct linear codes on the normalization is finding a basis of L( Q) having pairwise distinct pole orders at Q, where Q is the unique place of the Cab curve at infinity. We present an algorithm finding such a basis from defining equations of the normalization of the original Cab curve.

This paper describes an efficient simulator for state transition analysis of multivalued continuous-time neural networks, where the multivalued transfer function of neuron is regarded as a stepwise constant one. Use of stepwise constant method enables to analyse the state transition of the network without solving explicitly the differential equations. This method also enables to select the optimal timestep in numerical integration. The proposed method is implemented on the simulator and applied to the general neural network analysis. Furthermore, this is compared with the conventional simulators. Finally, it is shown that our simulator is drastically faster and more practical than the conventional simulators.

Recently, many on-line control methods of partially observed discrete event systems(DES's) have been proposed. This paper proposes an algorithm for on-line control based on a supervisor under complete observation. It is shown that DES's controlled by the proposed on-line controller generate maximally controllable and observable sublanguages which include the supremal normal sublanguages. Moreover, computational complexity of the proposed algorithm is polynomial with respect to the numbers of the unobservable events and the state of the supervisor under complete observation.

An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

We developd a method of implementing a multiple-valued Hopfield network on electronic circuits by using single-electron circuit technology. The single-electron circuit shows quantized behavior in its operation because of the discrete tunnel transport of electrons. It can therefore be successfully used for implementing neuron operation of the multiple-valued Hopfield network. The authors developed a single-electron neuron circuit that can produce the staircase transfer function required for the multiple-valued neuron. A method for constructing a multiple-valued Hopfield network by combining the neuron circuits was also developed. A sample network was designed that solves an example of the quadratic integer-programming problem. And a computer simulation demonstrated that the sample network can converge to its optimal state that represents the correct solution to the problem.

A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.