In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.

This letter proposes an efficient implementation method for a binary feedback switch, called EFCI/RELAY, which can reduce the feedback delay of the congestion status of a switch in multiple-hop network environments. At each transit switch, this method relays the EFCI-bit contained in an incoming data cell to the head-of-line cell with a corresponding VC which is waiting for transmission in the output buffer. Simulation results show that the proposed method can achieve a lower queue length while maintaining a higher link utilization.

In this paper, we introduce a lower bound for the generalized Hamming weights, which is applicable to arbitrary linear code, in terms of the notion of well-behaving. We also show that any [n,k] linear code C over a finite field F is the t-th rank MDS for t such that g(C)+1 t k where g(C) is easily calculated from the basis of Fn so chosen that whose first n-k elements generate C. Finally, we apply our result to Reed-Solomon, Reed-Muller and algebraic geometry codes on Cab, and determine g(C) for each code.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

This paper presents a method of calculating an interval including a bifurcation point. Turning points, simple bifurcation points, symmetry breaking bifurcation points and hysteresis points are calculated with guaranteed accuracy by the extended systems for them and by the Krawczyk-based interval validation method. Taking several examples, the results of validation are also presented.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

A variable partition duplex scheme on packet reservation multiple access protocol (VPD-PRMA) is analyzed in this paper. We assume a four-state speech model for a conversational pair and successfully obtain performance measures by approximate Markovian analysis. Analytical results show that they quite fit simulation results; and VPD-PRMA can get higher statistical multiplexing gain than fixed partition duplex (FPD)-PRMA, due to the trunking effect. We further investigate the effect of design parameters of permission probability and enlarged reservation duration on system performance by computer simulation. Simulation results shows that it exists appropriate values for these two design parameters so that the packet dropping probability can be minimized. The adjustment of permission probability can greatly improve the performance of uplink traffic with slight deterioration of the performance of downlink traffic; the provision of enlarged reservation duration scheme can enhance the system performance.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

In practical logic design circuits are built by composing certain types of gates. Each gate itself is a simple circuits with one, two or three inputs and one output, which implements an elementary logic function. These functions are called the generators. For the general purpose the set of generators is considered to be functionally complete, i. e. , it is able to express any logic function under chosen rules compositions. A basis is a functionally complete set of logic functions that contains no complete proper subset. Providing compactness and expressibility of the generators the notion of a basis, however, ignores the optimality of implementations. Efficiently irreducible generating set, termed ε-basis, is an irreducible set of generators which guarantees an optimal implementation of every function, with respect to the number of literals in its formal expression. The notion of ε-basis is significant in the composition of functions, since the classical definition of basis does not consider the efficiency of implementation. In case of Boolean functions, for two-input (dyadic) generators it has been shown that an ε-basis consists of all monadic functions, constants, and only two dyadic functions from certain classes. In this paper, expanding the domain of basic operations from dyadic to triadic, we study the efficiency of sets of 3-input gates as generators. This expansion decreases the complexity of functions (hence, the complexity of functional circuits to be designed). Gaining an evident merit in the complexity, we have to pay a price by a considerable increase of the number of such generators for the multiple valued circuits. However, in the case of Boolean operations this number is still very small, and it will certainly be useful to consider this approach in the practical circuit design. This paper provides a criterion for a generating set of triadic operations of k-valued logic to be efficiently irreducible. In the case of Boolean functions it is shown that there exist exactly five types of classes of triadic operations which constitute an ε-basis. A typical example of generator set which forms a triadic ε-basis, is also shown.

We study ultrafast operation of multiple-valued quantizers composed of resonant-tunneling diodes (RTDs) and high electron mobility transistors (HEMTs). The operation principle of these quantizers is based on the monostable-multistable transition logic (MML) of series-connected RTDs. The quantizers are fabricated by monolithically integrating InP-based RTDs and 0.7-µm-gate-length HEMTs with a cutoff frequency of 40 GHz. To perform high-frequency experiments, an output buffer and termination resistors are attached to the quantizers, and the quantizers are designed to accommodate high-frequency input signals. Our experiments show that both ternary and quaternary quantizers can operate at clock frequencies of 10 GHz and at input frequencies of 3 GHz. This demonstrates the potential of applying RTD-based multiple-valued quantizers to high-frequency circuits.

In this paper, we propose a CASE tool platform for Java, called Japid. A CASE tool platform provides various information of source programs and helps CASE tool developers to develop their tools rapidly and easily. Japid has three advanced features: linking fine grained databases dynamically, permitting developers to define their own views, and changing source programs preserving syntactic and semantic constraints. We have made some experiments and developed some CASE tools to show effectiveness of our approach.

When the degree of intersections A B of events A, B is unknown arises a problem: how to evaluate the probability P(A B) and P(A B) from P(A) and P(B). To treat related problems two models of valuation: interval and paired probabilities are proposed. It is shown that the valuation corresponding to the set operations (intersection), (union) and (complement) can be described by the truth functional (AND), (OR) and (negation) operations in both models. The probabilistic AND and OR operations are represented by combinations of Kleene and Lukasiewicz operations, and satisfy the axioms of MV (multiple-valued logic)-Algebra except the complementary laws.

This paper considers methods to design multiple-output networks based on decision diagrams (DDs). TDM (time-division multiplexing) systems transmit several signals on a single line. These methods reduce: 1) hardware; 2) logic levels; and 3) pins. In the TDM realizations, we consider three types of DDs: shared binary decision digrams (SBDDs), shared multiple-valued decision diagrams (SMDDs), and shared multi-terminal multiple-valued decision diagrams (SMTMDDs). In the network, each non-terminal node of a DD is realized by a multiplexer (MUX). We propose heuristic algorithms to derive SMTMDDs from SBDDs. We compare the number of non-terminal nodes in SBDDs, SMDDs, and SMTMDDs. For nrm n, log n, and for many other benchmark functions, SMTMDD-based realizations are more economical than other ones, where nrm n is a (2n)-input (n1)-output function computing (X2+Y2)+0.5, log n is an n-input n-output function computing (2n1)log(x1)/nlog2, and a denotes the largest integer not greater than a.

This paper presents a new approach to designing arithmetic circuits by using a graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG). The key idea of the proposed method is to introduce a higher level of abstraction for arithmetic algorithms, in which arithmetic circuit structures are modeled as data-flow graphs associated with specific number representation systems. The EGG system employs evolutionary operations to transform the structure of graphs directly, which makes it possible to generate the desired circuit structure efficiently. The potential capability of EGG is demonstrated through an experiment of generating constant-coefficient multipliers.

In this paper, we consider the working VP and backup VP routing problems jointly and employ the integer programming based approach to maximize the system resource utilization and the network survivability. The VP planning problem is formulated as a nonlinear combinatorial optimization problem. The objective function minimizes the resource usage while maximizing the network survivability. By proper transformation of the objective function and applying cutting plane method, the original formulation is transformed into an integer linear programing formulation which is suitable for applying Lagrangian relaxation techniques. After Lagrangian relaxation, the problem is further decomposed into several tractable subproblems. Unlike others' work, the candidate path set does not need to be prepared in advance and the best paths are generated while solving subproblems in our approach. Heuristic algorithms based on the solving procedure of the Lagrangian relaxation are developed. Closely examining the gap between the heuristic upper bounds and the Lagrangian lower bounds reveals that the proposed algorithm can efficiently provide a nearly optimal solution for the survivable VP layout design in ATM networks.

We present a new method for estimation of spectrum transition of nonstationary signals in cases of low signal-to-noise ratio (SNR). Instead of the basic functions employed in the previously proposed time-varying autoregressive (AR) modeling, we introduce a spectrum transition constraint into the cost function described by the partial correlation (PARCORR) coefficients so that the method is applicable to noisy nonstationary signals of which spectrum transition patterns are complex. By applying this method to the analysis of vibration signals on the interventricular septum (IVS) of the heart, noninvasively measured by the novel method developed in our laboratory using ultrasonics, the spectrum transition pattern is clearly obtained during one cardiac cycle for normal subjects and a patient with cardiomyopathy.

In the basic user/network interface of ISDN (ITU-T Recommendation I. 430), the D-channel is shared by up to 8 terminals for signal and data packets. An analytical model is proposed to reveal the performance characteristics of the access control scheme for the D-channel. Numerical and simulation results are shown to demonstrate the performance differentiation of the terminals with different priorities. It is observed that the mean signal delay at low load may become large because of long service time for packets, and that the priority mechanism may not work properly when the loads at terminals are very asymmetric.

The self-healing capability against network failure is one of indispensable features for the B-ISDN infrastructure. One problem in realizing such self-healing backbone network is the inefficient utilization of the large spare capacity designed for the failure-restoration purpose since it will be used only in the failure time that does not occur frequently. "Pool-capacity" is the concept that allows some VPs (virtual paths) to efficiently utilize this spare capacity part. Although the total capacity can be saved by using the "Pool Capacity," it is paid by less reliability of VPs caused by the emerging influence of indirect-failure. Thus, this influence of indirect-failure has to be considered in the capacity designing process so that network-designers can trade off the saving of capacity with the reliability level of VPs in their self-healing networks. In this paper, Damage Rate:DR which is the index to indicate the level of the influence caused by indirect-failure is defined and the pool-capacity design scheme with DR consideration is proposed. By the proposed scheme, the self-healing network with different cost (pool-capacity) can be designed according to the reliability level of VPs.

A new method using new test structure, which is connected 15.4 million MOS transistor, for evaluating extrinsic oxide breakdown is proposed. The active gate area which is needed to predict reliability will be shown. And by using this new method, activation energy not only for the intrinsic breakdown but also for the extrinsic breakdown are obtained.