Recently, Yagisawa proposed a public key cryptosystem which is very similar to the modified Lu-Lee cryptosystem. The differences are the set of messages and the decryption. On the other hand, Brickell and Odlyzko showed that the modified Lu-Lee cryptosystem is completely broken in polynomial time. This paper shows that Yagisawa cryptosystem is completely broken in the same way.

In this paper, we show an entropy-based approach to the privacy of multi-party protocols. First, we formulate the amount of leaked information by using mutual information for a two-party case. This is a better measure for some situations than the combinatorial measure known so far. Next, we apply multi-terminal information theoty to more than two parties and give the first formulation of the leaked information for more than two parties.

The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

The fault tolerant computer (FTC) is applied as a communication or database server in the information service and computer aided process control fields. User requires of the FTC are to provide the current level of performance and software transparency needing no additional dedicated program for fault tolerance. To meet these requirements, we propose quadprocessor redundancy (QPR) architecture that combines dualRISC based duplicated CPUs integrating main memories, and duplicated I/O subsystems by using some additional hardware. Duplicated CPUs run under the instruction level synchronization (lock step operation) , and the duplicated I/O subsystems are managed by an operating system. When a fault is detected, the faulty CPU is isolated by hardware. User program is continuously executed by the remaining CPU. We applied the QPR to our UNIX servers, and achieved satisfactory levels of performance.

In this paper, we present a first step for developing a method of verifying both safety and correctness of object-oriented design specification. At first, we analyze the discrepancies, which can occur between requirements specification and design specification, to make clear target faults. Then, we propose a new design review method which aims at detecting faults in the design specification by using three kinds of information tables. Here, we assume that component library, standards for safety and design specification obtained from the Booch's object-oriented design method are given. At the beginning, the designers construct a design table based on a design specification, and the verifiers construct a correctness table and a safety table from component library and standards for safety. Then, by comparing the items on three tables, the verifiers review a given design specification and detect faults in it. Finally, using a small example of object-oriented design specification, we show that faults concerning safety or correctness can be detected by the new design review method.

In this paper we propose a method of formal verification of totally self-checking (TSC) properties of combinational circuits using logic function manipulation. We show that the problem of verification of TSC properties can be transformed to a satisfiability problem of decision functions formed from characteristic functions of a circuit's output code words. Then the problem can be solved using binary decision diagrams (BDD). Experimental results show the effectiveness of the proposed method.

In this paper, we discuss the principle of the clumsy painter method proposed for extracting interested regions from image signals automatically. We theoretically clarify the reason why the clumsy painter method is effective so well. We compare its algorithm with the opening operation in mathematical morphology, and prove that the clumsy painter method has the advantage over the opening operation in mathematical morphology on removing uninterested regions from image signals. Simulating these two methods on two simple geometrical models, we show that the extracted redults by the opening operation are included in those by the clumsy painter method.

This paper presents the performance of a proposed GaAs MESFET photodetector with wide drain-to-gate distances for improving the optical coupling efficiency in subcarrier optical transmission. Principle and design parameters of the proposed MESFET are described. Link gain, CNR, and BER, are experimentally investigated as functions of the drain-to-gate distance. It is experimentally found that the proposed MESFET improves the link gain by 8.5 dB compared to the conventional structure at the subcarrier frequency of 140 MHz. Discussions are also included compared to PIN-PD.

Preliminary experiments on non-destructive quantitative analysis of water vapor density in halogen lamps have been carried out. A working curve showing a relation between absorbance and water vapor density was successfully obtained by using frequency-stabilized InGaAsP/InP semiconductor laser spectrometric system.

A slotted waveguide planar array using a single-layer feed circuit is applied to high frequency and high gain use. The remarkable efficiency of 75.6% is realized for the gain of 35.9 dBi in 22 GHz band and 64% is realized for 35.1 dBi in 60 GHz band. Each antenna consists of only two components; a slotted plate and a groove base plate, and are highly mass produceable.

In this paper, the bit error rate (BER) performance of the Spread Spectrum communication system with Constrained Spreading Codes (SS-CSC) is analyzed. The BER of the SS-CSC system is the same as that of the Bi-orthogonal system. Moreover, the frequency utilization efficiency of the SS-CSC system is better than that of the Bi-orthogonal system when K 10 and N = 3.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.

In this paper, an exact-minimization method for an AND-EXOR expression (ESOP) using O-suppressed binary decision diagrams (ZBDDs) is considered. The proposed method is an improvement of Sasao's MRCF-based method. From experimental results, it is shown that required ZBDD size is reduced to 1/3 in the best case compared with the MRCF-based method.

A generalized Reed-Muller expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM). There are at most 2(n2)^(n-1) different GRMs for an n-variable function. A minimum GRM is one with the fewest products. This paper presents certain properties and an exact minimization algorithm for GRMs. The minimization algorithm uses binary decision diagrams. Up to five variables, all the representative functions of NP-equivalence classes were generated and minimized. Tables compare the number of products necessary to represent four-and five-variable functions for four classes of expressions: PPRMs, FPRMs, GRMs and SOPs. GRMs require, on the average, fewer products than sum-of-products expressions (SOPs), and have easily testable realizations.

A complex fuzzy adaptive decision feedback equalizer based on the RLS algorithm is proposed. The proposed equalizer not only improves the performance but also reduces the computational complexity compared with the conventional complex fuzzy adaptive equalizers under the assumption of perfect knowledge of the linear and nonlinear channels.

This paper examines the performance of a direct sequence, spread spectrum (DSSS) multiple access (MA) system used over two typical, frequency-selective, fading satellite channels. In an attempt to increase the system efficiency, an adaptive receiver described by Rapajic and Vucetic [1] has been implemented. This system has been combined with soft-decision convolutional coding in order to improve the system performance under the fading conditions relative to the uncoded system and to allow as many simultaneous users as possible. Various code rates have been examined and the results are given. This paper specifically focuses on DSSS-MA systems with low spreading ratios. The satellite channels used in this paper were produced by models developed as a result of experimental measurements of fading satellite channels for rural and urban environments.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

A very simple but general scheme has been developed to calculate burst error occurrences due to cycle slip in clock recovery on frequency-selective Nakagami-Rice fading channels. The scheme, which we call the "Equivalent Transmission-Path Model," plays a role in connecting "wave propagation" with "digital transmission characteristics" in a general manner. First computer simulations assuming various types of delay profiles identify the "key parameters in Nakagami-Rice fading" that principally dominate the occurrence of cycle slips. Following this a simple method is developed to calculate the occurrence frequency of cycle slips utilizing the nature of the key parameters. Then, the accuracy of the scheme is confirmed through comparison between calculated values and simulation results. Finally, based on the scheme, calculated results on cycleslip occurrences are presented in line-of-sight fading environments.

This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.

In this letter, we propose a blind adaptive receiver with nonlinear structure for DS/CDMA communication systems. The proposed receiver requires the signature waveform and timing for only the desired user. It is shown that the blind adaptation is equivalent to the adaptation with the training signal and the function to be minimized has no local minima.