In order to highlight a rapid progress attained in the field of millimeter waves in Japan, this paper describes several key topics including transistors, integrated circuits, planar antennas, millimeter wave photonics, and others.

Transport-processing FPGAs have been proposed for flexible telecommunication systems. Since those FPGAs have finer granularity of logic functions to implement circuits on them, the amount of routing resources tends to increase. In order to keep routing congstion small, it is necessary to execute placement and routing simultaneously. This paper proposes a simultaneous placement and global routing algorithm for transport-processing FPGAs whose primary objective is minimizing routing congestion. The algorithm is based on hierarchical bipartition of layout regions and sets of LUTs (Look Up Tables) to be placed. It achieves bipartitioning which leads to small routing congestion by applying a network flow technique to it and computing a maximum flow and a minimum cut. If there exist connections between bipartitioned LUT sets, pairs of pseudo-terminals are introduced to preserve the connections. A sequence of pseudo-terminals represents a global route of each net. As a result, both placement of LUTs and global routing are determined when hierarchical bipartitioning procedures are finished. The proposed algorithm has been implemented and applied to practical transport-processing circuits. The experimental results demonstrate that it decreases routing congestion by an average of 37% compared with a conventional algorithm and achieves 100% routing for the circuits for which the conventional algorithm causes unrouted nets.

This paper analyzed the connection points of Main Distribution Frames (MDF), which are installed between outside plants and inside plants (service nodes). This paper also proposes a connecting system for forthcoming FITL (Fiber In The Loop) networks. NTT has developed the Subscriber Line Cross-Connecting Module (LXM) for the FITL network and will continue to introduce LXMs and deploy optic subscriber networks in big cities throughout Japan.

The pros and cons of CDMA as a multiple access scheme for third generation cellular mobile radio systems are considered. Main criteria are spectral efficiency and capacity, but also flexibility and costs.

Research and standardization activities on FPLMTS are under way throughout the world. This paper shows recent study results on radio transmission technologies in ARIB (Association of Radio Industries and Businesses), which in the standardization organization in Japan. On-going study shows two TDMA based and four CDMA based radio transmission technologies under study. These technologies need to be further studied in detail. The proposal from ARIB is expected to be summarized around the end of the year 1996.

In this paper, we describe effects of oddcorrelation functions and band-limitation filters for direct-wave reception systems using broadband spread-spectrum (B-SS) techniques. The receiver of this system is synchronized to the direct-wave. First, the effects of odd-correlation functions are investigated by using M-sequences and random sequences. The effects of even-correlation functions for those sequences can be easily obtained by using results of effects of odd-correlation functions for random sequences. Here we derive a novel function of odd-correlation variance for M-sequence, which is obtained theoretically. Consequently, we show the advantage of M-sequence which is used as spreading sequence. As a reason, in the odd-correlation function of M-sequence, small values are taken near the synchronous phase where harmful scattered-waves exist, strongly. Next, the effects of both odd-correlation function and band-limitation filter are studied by using several kinds of filters. Here we discuss the difference of characteristics in case that despreading sequence of bandlimited pulse or that of rectangular pulse is used in the correlator of the receiver. The technique despreading by rectangular pulse can be achieved a high speed signal processing and equipment miniaturizing because of utilization of switching circuit. We show the advantage of despreading sequence of rectangular pulse, when the limitation bandwidth of transmitting signal takes a small value. Because the characteristics of the correlation function between transmitting sequence of bandlimited pulse and despreading sequence of rectangular pulse can be kept better than that between the transmitting sequence and despreading sequence of bandlimited pulse. As these results, in severe bandlimited direct-wave reception systems using B-SS techniques, M-sequence of rectangular pulse as despreading sequence is most suitable.

In this paper, the bit error rate (BER) considering tracking performance is evaluated, by theoretical analysis and computer simulation, for a bi-orthogonal system using a synchronizing pseudo-noise (PN) sequence and co-channel interference cancellers. A system that improves on Tachikawa's system is proposed. It is found that the optimum ratio of the information signal energy to the synchronizing signal energy varies with Eb/No, and the canceller is better for small L than for large L (L = length of the sequence). Moreover, it is found that the BER considering synchronization performance improvse as the equivalent noise bandwidth Bn decreases.

In this contribution an algorithm for joint detection in fast frequency hopping/multiple frequency shift keying (FFH/MFSK) multiple access (MA) systems is presented. The new algorithm - referred to as REC algorithm - evaluates ambiguities which occur during the decision process and iteratively reduces the number of candidate symbols. The REC algorithm is of low complexity, suitable for every addressing scheme, and effective for both an interference-only channel and a fading channel. For the interference-only channel the REC algorithm enables maximum likelihood (ML) joint detection with low computational effort.

A simplified analysis is presented for the reverse link capacity of DS-CDMA mobile radio with transmit power control (TPC) based on measurement of signal-to-interference plus background noise (SIR) when users require different levels of quality. The link capacity is defined as the maximum achievable sum of the required SIRs, and the increase in transmit power due to SIR-based TPC is discussed. Also analyzed is the total link capacity when narrowband DS-CDMA systems share the radio spectrum of a wideband system. The capacity loss due to non-uniform use of the spectrum is discussed.

The one of the problems in the satellite packet communication system is the existence of a long time delay, which may cause an improper packet access control resulting in a great deal of degradation of the system performance. In this paper, we clarify the effect of long time delay on the performance of CDMA ALOHA systems and then propose a new access control protocol, called Modified Channel Load Sensing Protocol (MCLSP), for the CDMA ALOHA systems. As a result, we show that a significant improvement in the throughput performance was obtained with MCLSP even in the presence of a long time delay.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

Recently, various efficient algorithms for solving combinatorial optimization problems using BDD-based set manipulation techniques have been developed. Minato proposed O-suppressed BDDs (ZBDDs) which is suitable for set manipulation, and it is utilized for various search problems. In terms of practical limits of space, however, there are still many search problems which are solved much better by using conventional branch-and-bound techniques than by using BDDs or ZBDDs, while the ability of conventional branch-and-bound approaches is limited by computation time. In this paper, an extension of APPLY operation, named APPRUNE (APply + PRUNE) operation, is proposed, which performs APPLY operation (ZBDD construction) and pruning simultaneously in order to reduce the required space for intermediate ZBDDs. As a prototype, a specific algorithm of APPRUNE operation is shown by assuming that the given condition for pruning is a threshold function, although it is expected that APPRUNE operation will be more effective if more sophisticated condition are considered. To reduce size of ZBDDs in intermediate steps, this paper also pay attention to the number of cared variables. As an application, an exact-minimization algorithm for generalized Reed-Muller expressions (GRMs) is implemented. From experimental results, it is shown that time and memory usage improved 8.8 and 3.4 times, respectively, in the best case using APPRUNE operation. Results on generating GRMs of exact-minimum number of not only product terms but also literals is also shown.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

This paper presents a new method for the selftuning control of nonminimum phase discrete-time stochastic systems using approximate inverse systems obtained from the leastsquares approximation. Using this approximate inverse system the gain response of the system can be made approximately unit and phase response exactly zero. We show how unstable polezero cancellations can be avoided. This approximate inverse system can be used in the same manner for both minimum and nonminimum phase systems. Moreover, the degrees of the controller polynomials do not depend on the approximate inverse system. We just need an extra FIR filter in the feedforward path.

We propose a novel feeding circuit for a 30 GHz planar multibeam antenna applied to high-speed wireless communication systems. The feeding circuit is a bi-layer 8-port Butler matrix constructed with phase adjusted slot-coupled hybrids and branch-line hybrids. The new circuit configuration eliminates troublesome vias and line crossings, so it can be manufactured by traditional photolithograph. The feeding circuit is designed by using the spectral domain moment method considering bonding film effects. A prototype of a multibeam antenna which has seven pencil-beams with 10 beamwidths is manufactured and tested; the beam scan angle error is less than 3 at 30 GHz.

An important aspect of traffic safety is the development of aids that extend the driver's time and motion perception. One promising candidate is the compact, lightweight millimeter-wave FM-CW radar now being widely studied. Although the homodyne FM-CW radar is well known form its simplicity, it has a relatively low S/N ratio. This paper describes the principles behind our newly-developed heterodyne FM-CW radar and it's evaluation results. The heterodyne FM-CE radar generates sidebands by switching a front-end amplifier and also uses the heterodyne detection technique for gaining sensor sensitivity. The heterodyne FM-CW radar's signal to noise ratio was 19.5 dB better than previously designed homodyne FM-CW radar.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

High level power estimation model is indispensable to optimize architecture and programs in terms of power consumption systematically. This paper describes power analysis results of a general purpose programmable DSP using switch level and cell based power simulation. The analysis results help to know characteristics of the DSP components and to establish a power estimation model. A compensation method for the lack of intra-cell capacitance in a cell based simulation is proposed to improve the simulation accuracy within -20% of error against the measured power. We considered that the error is caused by ignoring short circuit current and is accurate enough for this level of simulation. Through a result of the power breakdown by modules of the DSP obtained by the simulation, it was found that bus power is much less than generally expected (the simulated power is less than 5% of the total), and that the data operation power dominates the chip power (up to 33%) and is strongly data dependent. The reason that the bus power is low is because both of the load capacitance and the activity are low. Some correlation between the number of input signal transitions and the power consumption is found in each of an ALU, register file, and multiplier through further investigation on the data operation modules. The correlation is worthwhile to establish a power estimation model and is eventually useful to optimize a DSP architecture and DSP programs. The importance of power estimation model is demonstrated by showing an example in which we optimize an FIR filter program based upon the analysis results and proposed a direction of architecture optimization.

An embedded cache memory for low power RISC microprocessors is described. An automatic-power-save architecture (APSA) enables the cache memory to operate with high speed at high frequencies, and with low power dissipation at low frequencies. A pulsed word technique (PWT) and an isolated bit line technique (IBLT) reduce the power dissipation of the cache memory effectively. Using these three techniques, the power dissipation of the cache memory is reduced to almost 60% of the conventional cache memory at 60 MHz and to 20% at a clock frequency of 10 MHz. An 8 KByte test chip using 0.5 µm CMOS technology was fabricated, and it achieves 80 MHz operation at a supply voltage of 3.1 V, and 8 mW operation at a supply voltage of 2.5 V at 10 MHz.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.