Binary sequence pairs with optimal periodic correlation have important applications in many fields of communication systems. In this letter, four new families of binary sequence pairs are presented based on the generalized cyclotomy over Z5q, where q ≠ 5 is an odd prime. All these binary sequence pairs have optimal three-level correlation values {-1, 3}.

Quantum noise ultimately restricts the transmission distance in fiber communication systems using optical amplifiers. This paper investigates the quantum-noise-limited performance of optical binary phase-shift keying transmission using gain-saturated phase-sensitive amplifiers (PSAs) as optical repeaters. It is shown that coherent state transmission, where ultimately clean light in the classical sense is transmitted, and endless transmission, where the transmission distance is not restricted, are theoretically achievable under certain system conditions owing to the noise suppression effects of the gain-saturated PSA.

In an amusement park, an attraction-visiting route considering the waiting time and traveling time improves visitors' satisfaction and experience. We focus on Ising machines to solve the problem, which are recently expected to solve combinatorial optimization problems at high speed by mapping the problems to Ising models or quadratic unconstrained binary optimization (QUBO) models. We propose a mapping of the visiting-route recommendation problem in amusement parks to a QUBO model for solving it using Ising machines. By using an actual Ising machine, we could obtain feasible solutions one order of magnitude faster with almost the same accuracy as the simulated annealing method for the visiting-route recommendation problem.

In this letter, we will prove that chaotic binary sequences generated by the tent map and Walsh functions are i.i.d. (independent and identically distributed) and orthogonal to each other.

A feedforward (FF) network using ΔΣ modulators is investigated to implement a non-binary analog-to-digital (A/D) converter. Weighting coefficients in the network are determined to suppress the generation of quantization noise. A moving average is adopted to prevent the analog signal amplitude from increasing beyond the allowable input range of the modulators. The noise transfer function is derived and used to estimate the signal-to-noise ratio (SNR). The FF network output is a non-uniformly distributed multi-level signal, which results in a better SNR than a uniformly distributed one. Also, the effect of the characteristic mismatch in analog components on the SNR is analyzed. Our behavioral simulations show that the SNR is improved by more than 30 dB, or equivalently a bit resolution of 5 bits, compared with a conventional first-order ΔΣ modulator.

Z-complementary pairs (ZCPs) were proposed by Fan et al. to make up for the scarcity of Golay complementary pairs. A ZCP of odd length N is called Z-optimal if its zero correlation zone width can achieve the maximum value (N + 1)/2. In this letter, inserting three elements to a GCP of length L, or deleting a point of a GCP of length L, we propose two constructions of Z-optimal ZCPs with length L + 3 and L - 1, where L=2α 10β 26γ, α ≥ 1, β ≥ 0, γ ≥ 0 are integers. The proposed constructions generate ZCPs with new lengths which cannot be produced by earlier ones.

Ising machines have attracted attention as they are expected to solve combinatorial optimization problems at high speed with Ising models corresponding to those problems. An induced subgraph isomorphism problem is one of the decision problems, which determines whether a specific graph structure is included in a whole graph or not. The problem can be represented by equality constraints in the words of combinatorial optimization problem. By using the penalty functions corresponding to the equality constraints, we can utilize an Ising machine to the induced subgraph isomorphism problem. The induced subgraph isomorphism problem can be seen in many practical problems, for example, finding out a particular malicious circuit in a device or particular network structure of chemical bonds in a compound. However, due to the limitation of the number of spin variables in the current Ising machines, reducing the number of spin variables is a major concern. Here, we propose an efficient Ising model mapping method to solve the induced subgraph isomorphism problem by Ising machines. Our proposed method theoretically solves the induced subgraph isomorphism problem. Furthermore, the number of spin variables in the Ising model generated by our proposed method is theoretically smaller than that of the conventional method. Experimental results demonstrate that our proposed method can successfully solve the induced subgraph isomorphism problem by using the Ising-model based simulated annealing and a real Ising machine.

In this letter, we consider the incorrigible sets of binary linear codes. First, we show that the incorrigible set enumerator of a binary linear code is tantamount to the Tutte polynomial of the vector matroid induced by the parity-check matrix of the code. A direct consequence is that determining the incorrigible set enumerator of binary linear codes is #P-hard. Then for a cycle code, we express its incorrigible set enumerator via the Tutte polynomial of the graph describing the code. Furthermore, we provide the explicit formula of incorrigible set enumerators of cycle codes constructed from complete graphs.

Ising machines have attracted attention, which is expected to obtain better solutions of various combinatorial optimization problems at high speed by mapping the problems to natural phenomena. A slot-placement problem is one of the combinatorial optimization problems, regarded as a quadratic assignment problem, which relates to the optimal logic-block placement in a digital circuit as well as optimal delivery planning. Here, we propose a mapping to the Ising model for solving a slot-placement problem with additional constraints, called a constrained slot-placement problem, where several item pairs must be placed within a given distance. Since the behavior of Ising machines is stochastic and we map the problem to the Ising model which uses the penalty method, the obtained solution does not always satisfy the slot-placement constraint, which is different from the conventional methods such as the conventional simulated annealing. To resolve the problem, we propose an interpretation method in which a feasible solution is generated by post-processing procedures. We measured the execution time of an Ising machine and compared the execution time of the simulated annealing in which solutions with almost the same accuracy are obtained. As a result, we found that the Ising machine is faster than the simulated annealing that we implemented.

In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.

In this letter, the structural analysis of nonbinary cyclic and quasi-cyclic (QC) low-density parity-check (LDPC) codes with α-multiplied parity-check matrices (PCMs) is concerned. Using analytical methods, several structural parameters of nonbinary cyclic and QC LDPC codes with α-multiplied PCMs are determined. In particular, some classes of nonbinary LDPC codes constructed from finite fields and finite geometries are shown to have good minimum and stopping distances properties, which may explain to some extent their wonderful decoding performances.

Boolean networks (BNs) are considered as popular formal models for the dynamics of gene regulatory networks. There are many different types of BNs, depending on their updating scheme (synchronous, asynchronous, deterministic, or non-deterministic), such as Classical Random Boolean Networks (CRBNs), Asynchronous Random Boolean Networks (ARBNs), Generalized Asynchronous Random Boolean Networks (GARBNs), Deterministic Asynchronous Random Boolean Networks (DARBNs), and Deterministic Generalized Asynchronous Random Boolean Networks (DGARBNs). An important long-term behavior of BNs, so-called attractor, can provide valuable insights into systems biology (e.g., the origins of cancer). In the previous paper [1], we have studied properties of attractors of GARBNs, their relations with attractors of CRBNs, also proposed different algorithms for attractor detection. In this paper, we propose a new algorithm based on SAT-based bounded model checking to overcome inherent problems in these algorithms. Experimental results prove the effectiveness of the new algorithm. We also show that studying attractors of GARBNs can pave potential ways to study attractors of ARBNs.

The interval in ℕ composed of finite states of the stream version of asymmetric binary systems (ABS) is irreducible if it admits an irreducible finite-state Markov chain. We say that the stream version of ABS is irreducible if its interval is irreducible. Duda gave a necessary condition for the interval to be irreducible. For a probability vector (p,1-p), we assume that p is irrational. Then, we give a necessary and sufficient condition for the interval to be irreducible. The obtained conditions imply that, for a sufficiently small ε, if p∈(1/2,1/2+ε), then the stream version of ABS could not be practically irreducible.

We propose an effective 2d image based end-to-end deep learning model for malware detection by introducing a black & white embedding to reserve bit information and adapting the convolution architecture. Experimental results show that our proposed scheme can achieve superior performance in both of training and testing data sets compared to well-known image recognition deep learning models (VGG and ResNet).

Let m, k be positive integers with m=2k and k≥3. Let C(u, ν) is a class of cyclic codes of length 2m-1 whose parity-check polynomial is mu(x)mν(x), where mu(x) and mν(x) are the minimal polynomials of α-u and α-ν over GF(2). For the case $(u, u)=(1,rac{1}{3}(2^m-1))$, the weight distributions of binary cyclic codes C(u, ν) was determined in 2017. This paper determines the weight distributions of the binary cyclic codes C(u, ν) for the case of (u, ν)=(3, 2k-1+1). The application of these cyclic codes in secret sharing is also considered.

Recent years have witnessed a rapid increase in cyber-attacks through unauthorized accesses and DDoS attacks. Since packet classification is a fundamental technique to prevent such illegal communications, it has gained considerable attention. Packet classification is achieved with a linear search on a classification rule list that represents the packet classification policy. As such, a large number of rules can result in serious communication latency. To decrease this latency, the problem is formalized as optimal rule ordering (ORO). In most cases, this problem aims to find the order of rules that minimizes latency while satisfying the dependency relation of the rules, where rules ri and rj are dependent if there is a packet that matches both ri and rj and their actions applied to packets are different. However, there is a case in which although the ordering violates the dependency relation, the ordering satisfies the packet classification policy. Since such an ordering can decrease the latency compared to an ordering under the constraint of the dependency relation, we have introduced a new model, called relaxed optimal rule ordering (RORO). In general, it is difficult to determine whether an ordering satisfies the classification policy, even when it violates the dependency relation, because this problem contains unsatisfiability. However, using a zero-suppressed binary decision diagram (ZDD), we can determine it in a reasonable amount of time. In this paper, we present a simulated annealing method for RORO which interchanges rules by determining whether rules ri and rj can be interchanged in terms of policy violation using the ZDD. The experimental results show that our method decreases latency more than other heuristics.

In an OFDM communication system using quadrature amplitude modulation (QAM) signals, peak envelope powers (PEPs) of the transmitted signals can be well controlled by using QAM Golay complementary sequence pairs (CSPs). In this letter, by making use of a new construction, a family of new 16-QAM Golay CSPs of length N=2m (integer m≥2) with binary inputs is presented, and all the resultant pairs have the PEP upper bound 2N. However, in the existing such pairs from other references their PEP upper bounds can arrive at 3.6N when the worst case happens. In this sense, novel pairs are good candidates for OFDM applications.

In wireless multi-hop networks such as ad hoc networks and sensor networks, backoff-based opportunistic routing protocols, which make a forwarding decision based on backoff time, have been proposed. In the protocols, each potential forwarder calculates the backoff time based on the product of a weight and global scaling factor. The weight prioritizes potential forwarders and is calculated based on hop counts to the destination of a sender and receiver. The global scaling factor is a predetermined value to map the weight to the actual backoff time. However, there are three common issues derived from the global scaling factor. First, it is necessary to share the predetermined global scaling factor with a centralized manner among all terminals properly for the backoff time calculation. Second, it is almost impossible to change the global scaling factor during the networks are being used. Third, it is difficult to set the global scaling factor to an appropriate value since the value differs among each local surrounding of forwarders. To address the aforementioned issues, this paper proposes a novel decentralized local scaling factor control without relying on a predetermined global scaling factor. The proposed method consists of the following three mechanisms: (1) sender-centric local scaling factor setting mechanism in a decentralized manner instead of the global scaling factor, (2) adaptive scaling factor control mechanism which adapts the local scaling factor to each local surrounding of forwarders, and (3) mitigation mechanism for excessive local scaling factor increases for the local scaling factor convergence. Finally, this paper evaluates the backoff-based opportunistic routing protocol with and without the proposed method using computer simulations.

This paper constructs non-binary codes correcting a single b-burst of insertions or deletions with large cardinalities. This paper also provides insertion and deletion correcting algorithms of the constructed codes and evaluates a lower bound of the cardinalities of the constructed codes. Moreover, we evaluate a non-asymptotic upper bound on the cardinalities of arbitrary codes which correct a single b-burst of insertions or deletions.

Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit used in a 4-bit parallel multiplier demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.