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[Keyword] drive(222hit)

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  • Optical Receiver and Laser Driver Circuits Implemented with 0.35 µm GaAs JFETs

    Chiaki TAKANO  Kiyoshi TANAKA  Akihiko OKUBORA  Jiro KASAHARA  

     
    PAPER

      Vol:
    E75-C No:10
      Page(s):
    1110-1114

    We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.

  • LIBRA: Automatic Performance-Driven Layout for Analog LSIs

    Tomohiko OHTSUKA  Hiroaki KUNIEDA  Mineo KANEKO  

     
    PAPER

      Vol:
    E75-C No:3
      Page(s):
    312-321

    This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

221-222hit(222hit)