The globalization of commerce has increased the importance of retrieving and updating complex and distributed information efficiently. Web services currently show that the most promise for building distributed application systems and model-driven architecture is a new approach to developing such applications. The expanding scale and complexity of enterprise information systems (EISs) under distributed computing environments has made sharing and exchanging data particularly challenging. Data services are applications tailored specifically for information oriented tasks to deal with business service requirements, and are heavily dependent on the distributed architecture of consumer data processing. The implementation of a data service can eliminate inconsistency among various application systems in the exchange of data. This paper proposes a data-oriented model-driven developmental framework to deal with these issues, in which a platform independent model (PIM) is divided into a service model, a logic data model, and a service composition model. We also divide a platform specific model (PSM) into a physical data model and a data service model. In this development method, we define five meta-models and outline a set of rules governing the transformation from PIMs into PSMs. A code generator is also included to transform each PSM into the application code. We include a case study to demonstrate the feasibility and merits of the proposed development framework with a case study.

Yield-driven clock skew scheduling was previously formulated as a minimum cost-to-time ratio cycle problem, by assuming that variational path delays are in Gaussian distributions. However in today's nanometer technology, process variations show growing impacts on this assumption, as variational delays with non-Gaussian distributions have been observed on these paths. In this paper, we propose a novel yield-driven clock skew scheduling method for arbitrary distributions of critical path delays. Firstly, a general problem formulation is proposed. By integrating the cumulative distribution function (CDF) of critical path delays, the formulation is able to handle path delays with any distributions. It also generalizes the previous formulations on yield-driven clock skew scheduling and indicates their statistical interpretations. Generalized Howard algorithm is derived for finding the critical cycles of the underlying timing constraint graphs. Moreover, an effective algorithm based on minimum balancing is proposed for the overall yield improvement. Experimental results on ISCAS89 benchmarks show that, compared with two representative existing methods, our method remarkably improves the yield by 10.25% on average (up to 14.66%).

The proliferation of many-core architectures has led to the explosive development of parallel applications using programming models, such as OpenMP, TBB, and Cilk/Cilk++. With increasing number of cores, however, it becomes even harder to efficiently schedule parallel applications on these resources since current many-core runtime systems still lack effective mechanisms to support collaborative scheduling of these applications. In this paper, we study feedback-driven adaptive scheduling based on work stealing, which provides an efficient solution for concurrently executing a set of applications on many-core systems. To dynamically estimate the number of cores desired by each application, a stable feedback-driven adaptive algorithm, called SAWS, is proposed using active workers and the length of active deques, which well captures the runtime characteristics of the applications. Furthermore, a prototype system is built by extending the Cilk runtime system, and the experimental results, which are obtained on a Sun Fire server, show that SAWS has more advantages for scheduling concurrent parallel applications. Specifically, compared with existing algorithms A-Steal and WS-EQUI, SAWS improves the performances by up to 12.43% and 21.32% with respect to mean response time respectively, and 25.78% and 46.98% with respect to processor utilization, respectively.

The Liquid-crystal display (LCD) overdrive technique has been utilized to reduce motion blur on a display via a reduction in the response time. However, to measure the variation of the pixel amplitudes, it is necessary to store the previous frame using a large frame memory. To downscale the frame memory, block truncation coding (BTC) is commonly employed due to the simplicity of its implementation, even if some visual artifacts may occur for image blocks with high frequency components. In this paper, we present a multimode-multilevel BTC (MBTC) technique that improves performance while maintaining simplicity. To improve the visual quality, we uniquely determine the quantization level and coding mode of each block according to the distribution of the luminance and chrominance amplitudes. For a compression ratio of 6:1, the proposed method demonstrates higher coding efficiency and overdrive performance by up to 3.81 dB in the PSNR compared to other methods.

A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18 µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5 Gb/s data rate.

Initialize and weak-program erasing scheme is proposed to achieve high-performance and high-reliability Ferroelectric (Fe-) NAND flash solid-state drive (SSD). Bit-by-bit erase VTH control is achieved by the proposed erasing scheme and history effects in Fe-NAND is also suppressed. History effects change the future erase VTH shift characteristics by the past program voltage. The proposed erasing scheme decreases VTH shift variation due to history effects from ±40% to ±2% and the erase VTH distribution width is reduced from over 0.4 V to 0.045 V. As a result, the read and VPASS disturbance decrease by 42% and 37%, respectively. The proposed erasing scheme is immune to VTH variations and voltage stress. The proposed erasing scheme also suppresses the power and bandwidth degradation of SSD.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

In this letter, we propose a novel speech enhancement algorithm based on data-driven residual gain estimation. The entire system consists of two stages. At the first stage, a conventional speech enhancement algorithm enhances the input signal while estimating several signal-to-noise ratio (SNR)-related parameters. The residual gain, which is estimated by a data-driven method, is applied to further enhance the signal at the second stage. A number of experimental results show that the proposed speech enhancement algorithm outperforms the conventional speech enhancement technique based on soft decision and the data-driven approach using SNR grid look-up table.

In future mobile networks, the ever-increasing loads imposed by mobile Internet traffic will force the network architecture to be changed from hierarchical to flat structure. Most of the existing mobility protocols are based on a centralized mobility anchor, which will process all control and data traffic. In the flat network architecture, however, the centralized mobility scheme has some limitations, such as unwanted traffic flowing into the core network, service degradation by a single point of failure, and increased operational costs, etc. This paper proposes mobility schemes for distributed mobility control in the flat network architecture. Based on the Proxy Mobile IPv6 (PMIP), which is a well-known mobility protocol, we propose the three mobility schemes: Signal-driven PMIP (S-PMIP), Data-driven Distributed PMIP (DD-PMIP), and Signal-driven Distributed PMIP (SD-PMIP). By numerical analysis, we show that the proposed distributed mobility schemes can give better performance than the existing centralized scheme in terms of the binding update and packet delivery costs, and that SD-PMIP provides the best performance among the proposed distributed schemes.

This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7 µA quiescent current at no load, regulating the output at 1 V from a minimum 1.2 V supply. It is able to deliver up to 450 mA load current with a dropout of 200 mV. It can be stabilized using a 4.7 µF output capacitor with a 0.1 Ω ESR resistor. The maximum transient output voltage is 64.6 mV on the basis of a load step change of 450 mA/10 ns under typical condition. The full load transient response is less than 350 ns.

Railway operators adjust timetables, and accordingly reschedule rolling stock circulation and crew duties, when the train operations are disrupted by accidents or adverse weather conditions. This paper discusses the problem of rescheduling driver assignment to freight trains after timetable adjustment has been completed. We construct a network from the disrupted situation, and model the problem as an integer programming problem with set-covering constraints combined with set-partitioning constraints. The integer program is solved by column generation in which we reduce the column generation subproblem to a shortest path problem and such paths by utilizing data parallelism. Numerical experiments using a real timetable, driver scheduling plan and major disruption data in the highest-frequency freight train operation area in Japan reveal that our method provides a quality driver rescheduling solution within 25 seconds.

Dicode partial response signaling system over inductively-coupled channel has been developed to achieve higher data rate than self-resonant frequencies of inductors. The developed system operates at five times higher data rates than conventional systems with the same inductor. A current-mode equalization in the transmitter designed in a 90-nm CMOS successfully reshapes waveforms to obtain dicode signals at the receiver. For a 5-Gb/s signaling through the coupled inductors with a 120-µm diameter and a 120-µm distance, 20-mV eye opening was observed. The power consumption value of the transmitter was 58 mW at the 5-Gb/s operation.

This paper presents an improvement of the memory cell reliability by the memory cell VTH optimization of the ferroelectric (Fe)-NAND flash memory. The effects of the memory cell VTH on the reliability of the Fe-NAND flash memory are experimentally analyzed for the first time. The reliability is evaluated by the measured VTH shift due to the read disturb, program disturb and data retention. Three types of Fe-NAND flash memory cells, a positive, zero and negative VTH memory cell, are defined on the basis of the memory cell VTH. The middle of VTH of programmed and erased states is 1 V, 0 V and -0.3 V in a positive, zero and negative VTH memory cell, respectively. The VTH shift of the positive, zero and negative VTH memory cells show similar characteristics in the program/erase and the VPASS and VPGM disturbs because the external electric field is so high that the internal depolarization field does not affect the VTH shift. On the other hand, in the data retention, the VTH shift of the three types of VTH memory cells show different characteristics. The reliability of the Fe-NAND flash memory is best optimized in the zero VTH memory cell. In the proposed zero VTH Fe-NAND flash memory cell scheme, the measured VTH shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively, compared with conventional positive VTH Fe-NAND flash memory cell scheme. Contrarily, in the negative VTH memory cell, the VTH shift during the data retention is 0.49 V and unacceptably large because of the depolarization field. The conventional positive VTH memory cell suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND flash memory cell where the negative VTH memory cell is most suitable in terms of the reliability.

AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

A broadband balanced frequency doubler has been demonstrated in 0.25-µm SOI SiGe BiCMOS technology to operate from 22 GHz to 30 GHz. The measured fundamental frequency suppression of greater than 30 dBc is achieved by an internal low pass LC filter. In addition, a pair of matching circuits in parallel with the LO inputs results in high suppression with low input drive power. Maximum measured conversion gain of -6 dB is obtained at the input drive power as low as -1 dBm. The results presented indicate that the proposed frequency doubler can operate in broadband and achieve high fundamental frequency suppression with low input drive power.

To reduce the inaccuracy caused by inappropriate time window, we propose two probabilistic fault localization schemes based on the idea of "extending time window." The global window extension algorithm (GWE) uses a window extension strategy for all candidate faults, while the on-demand window extension algorithm (OWE) uses the extended window only for a small set of faults when necessary. Both algorithms can increase the metric values of actual faults and thus improve the accuracy of fault localization. Simulation results show that both schemes perform better than existing algorithms. Furthermore, OWE performs better than GWE at the cost of a bit more computing time.

This paper presents the design of a driver amplifier (DA) for a cordless mouse application, operating at the 2.4 GHz ISM unlicensed band. The DA is a single-ended topology, and is composed of two stages: the first stage is a cascode amplifier to provide high gain and good input-output isolation, while the output stage is a simple common source amplifier that adopts a novel current reuse scheme to reduce the DC bias current by half. The DA implemented in a 0.18 µm CMOS process has a 16 dB gain at 2.4 GHz, and it can drive a 3 dBm to the antenna with an output stage drain efficiency of 31% and a power-added efficiency (PAE) of 20% while drawing 4.5 mA from a 1.8 V supply.

Context-aware applications are a key aspect of pervasive computing. The core issue of context-aware application development is how to make the application behave suitably according to the changing context without coupling such context dependencies in the program. Several programming paradigms and languages have been proposed to facilitate the development, but they are either lack of sufficient flexibility or somewhat complex for programming and deploying. A reference programming model is proposed in this paper to make up inadequacy of those approaches. In the model, virtual tables constructed by system and maintained by space manager connect knowledge of both developer and space manager while separating dependency between context and application logic from base program. Hierarchy and architecture of the model are presented, and implementation suggestions are also discussed. Validation and evaluation show that the programming model is lightweight and easy to be implemented and deployed. Moreover, the model brings better flexibility for developing context-aware applications.

The structure of the nanograting channel MOSFET was optimized by simply rounding the corners of the nanogratings. The current drivabilities of the optimized nanograting channel MOSFETs were enhanced by about 20% and 50% for both n-channel and p-channel MOSFETs, respectively. The mobility changes were analyzed on the basis of channel stress as well as theoretical change of mobilities by various surface orientations. The internal compressive stress of 0.23% was measured in the channel. By suppressing the electric field increase at the corner edge of the nanograting channel to less than 10%, the fabricated rounded nanograting MOSFETs achieved lifetimes of NBTI and TDDB as long as those of conventional planar devices.